The Bi-directional port consists of a name field, a direction arrow, and a value. Using the Selection
arrow, double click on the name or value to open a dialog box to change the name, value, and number of
bits. To view the signal strength, you must use the logic probe tool.</P>
This is a generic element which can be used to increase the output current capability of a device, and
can also be used to add an arbitrary delay to a wire. </P>
The connections for bus connectors can be explicitly specified in the set properties dialog. For example,
if you have a 1-to-2 bus combiner, and you want bit 0 of the net to go onto the lower pin of the bus connector,
and bit 1 of the net to go to the upper pin, you can specify this... or you can have it perform its default
distribution. Multiple bits can be specified for each pin, using colons and commas to group bits.</P>
The button is a standard 1 bit input part. Click on it to toggle the value.</P>
The clock device provides a pulsing input. By double clicking on a clock device, you can bring up a dialog
box which allows you to change its name, period, and pulse width. The pulse width is the time interval
for which the pulse is at its logic high level.</P>
If both set_bar=1 and reset_bar=1, and clock=0 then the outputs don't change. Only when set_bar=1 and
reset_bar=1 and clock=1 do the synchronous set and synchronous reset inputs become active.</P>
The clock (c1) is called the controlling input. The inputs labeled with "1", 1s and 1r, are
called the affected inputs. Set_bar and reset_bar are not affected by the clock. The clocked SR latch
is not a standard component that you can find on a chip. Its delays are arbitrarily set to 20ns.</P>
Ground is a logic level of zero. It corresponds to "off", or zero volts.</P>
Vcc is a logic level of one. It corresponds to "on", or 5 volts.</P>
The Pull Up Resistor is also a logic level of one, but it is of resistive strength, which is weaker than
the strength of Vcc, but stronger than high impedance. Pull-ups are useful in circuitry with open collector
outputs. </P>
The decoder is very similar to the demultiplexer. The select lines form a three bit binary number, CBA.
This three bit number specifies which output is set to high (1) while the others stay low. This component
is not found on a chip. In practice, use the Demultiplexer instead. The Prop delays have been arbitrarily
set to 20ns.</P>
The DIP has 8 output pins, each of which is controlled by a switch. Click on the individual switches
to change the output pins.</P>
This is a generic edge-triggered D flip flop. See the 7474 for its operational characteristics.</P>
The input port consists of a name, an up arrow, a down arrow, and a value. Double click on the input
(but not on the arrows), and you can edit the name and value and number of bits. Click on the up and
down arrows with the selection tool to increment and decrement the value. The value is displayed in base
16.</P>
This is a generic edge-triggered JK flip flop. See the 7476 JK flip flop for its operational characteristics.</P>
The keypad is a 4 bit part with 4 output pins and a hold pin. Click on the keypad to choose an output
value. The hold time can be set by double clicking on the keypad.</P>
The light bulb is an output probe. The light turns on when the input value is 1 and turns off when the
input value is otherwise.</P>
The output port consists of a name field and a value. Using the Selection arrow, double click on the
output to set the name of the port. Using the typing tool, click once on the name to edit it. The number
outside of the probe is the width of the bus coming into the probe. The value in the port window is displayed
in base 16. The possible values for single bit outputs are 1 for high voltage, 0 for low voltage, and
? for indeterminate, and Z for high impedance values. To view the signal strength, you must use the logic
probe tool.</P>
In Subcircuits, signal probes are available in place of output ports. Signal probes are functionally
the same as output ports.</P>
A PLD is a user-defined device. You specify a function table, and the PLD becomes a realization of that
function table. An example follows. PLD's can be used to reduce the number of chips on a board by putting
complex functions on a single chip. </P>
|
days0</P> | <TD WIDTH="46">
days1</P></TD><TD WIDTH="46">
days2</P></TD><TD WIDTH="47">
days3</P></TD><TD WIDTH="54">
days4/</P></TD><TD WIDTH="33">
D0</P></TD><TD WIDTH="33">
D1</P></TD><TD WIDTH="33">
D2</P></TD><TD WIDTH="35">
D3</P></TD>
<TR><TD WIDTH="49">
0</P></TD><TD WIDTH="46">
0</P></TD><TD WIDTH="46">
1</P></TD><TD WIDTH="47">
1</P></TD><TD WIDTH="54">
1/</P></TD><TD WIDTH="33">
1</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="35">
0</P></TD></TR>
<TR><TD WIDTH="49">
1</P></TD><TD WIDTH="46">
0</P></TD><TD WIDTH="46">
1</P></TD><TD WIDTH="47">
1</P></TD><TD WIDTH="54">
1/</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
1</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="35">
0</P></TD></TR>
<TR><TD WIDTH="49">
0</P></TD><TD WIDTH="46">
1</P></TD><TD WIDTH="46">
1</P></TD><TD WIDTH="47">
1</P></TD><TD WIDTH="54">
1/</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
1</P></TD><TD WIDTH="35">
0</P></TD></TR>
<TR><TD WIDTH="49">
1</P></TD><TD WIDTH="46">
0</P></TD><TD WIDTH="46">
1</P></TD><TD WIDTH="47">
1</P></TD><TD WIDTH="54">
1/</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="33">
0</P></TD><TD WIDTH="35">
1</P></TD></TR></TABLE>
</P>
See the section dedicated to <A HREF="PLD.htm">PLD\92s</A>
for a more thorough discussion.</P>
RAM 16x4
</P>
The RAM is capable of storing 16 4-bit words.</P>
This is a 16-word x 4-bit Read Write memory. R/W_Bar is a mode selector. When it is high, the data at
the specified address appears at data_out. When it is low, data is written from data_in into the memory
location specified by "address".</P>
The device only operates when it is selected (enable_bar is low). This device has 3-state outputs. Its
delays have been set at 25ns.</P>
RAM 1024x8
</P>
The RAM is capable of storing 1K 8-bit words.</P>
This is a Read Write memory. R/W_Bar is a mode selector. When it is high, the data at the specified
address appears at data_out. When it is low, data is written from the inputs into the memory location
specified by Addr.</P>
The device only operates when it is enabled. When it's disabled, the three state outputs go to their
high impedance state.</P>
RAM 4Kx8
</P>
This RAM is capable of storing 4K 8-bit words.</P>
This is a Read Write memory. R/W_Bar is a mode selector. When it is high, the data at the specified
address appears at data_out. When it is low, data is written from the inputs into the memory location
specified by Addr.</P>
The device only operates when it is enabled. When it's disabled, the three state outputs go to their
high impedance state.</P>
ROM 32x8 (read-only memory)
</P>
You determine it's behavior by defining a data file with two columns which correspond to addresses and
data (see custom devices). All values should be in hexadecimal. When the device is enabled (enable_bar
is zero), the data at the specified address appears at data_out. The triangle at the output stands for
a three-state buffer. When the device is disabled, it will behave as if it were not there. This is useful
if many devices are connected to a single bus, and only one of the devices will be enabled at a time.
Its delays have been set at 25ns.</P>
ROM 256x32 (read-only memory)
</P>
This ROM is capable of storing 256 32-bit words. You determine it's behavior by defining a data file
with two columns which correspond to addresses and data (see custom devices). All values should be in
hexadecimal. When the device is enabled (enable_bar is zero), the data at the specified address appears
at data_out. The triangle at the output stands for a three-state buffer. When the device is disabled,
its outputs become high-impedance. This is useful if many devices are connected to a single bus, and
only one of the devices will be enabled at a time.</P>
ROM 4Kx8 (read-only memory)
</P>
This ROM is capable of storing 4K bytes. You specify it's behavior by associating it with a data file
with two columns which correspond to addresses and data (see custom devices). All values should be in
hexadecimal. When the device is enabled (enable_bar is zero), the data at the specified address appears
at data_out. When the device is disabled, the outputs will be high-impedance.</P>
S'R' Latch
</P>
If s'=0 and r'=1, the latch is set (i.e. Q=1). If s'=1 and r'=0, the latch is reset (i.e. Q=0). If both
inputs are 1, then the outputs don't change from the previous state. If both inputs are 0, then the result
is unknown.</P>
Seven Segment Display
</P>
The Seven Segment display imitates a digital seven segment display. Each of the seven inputs corresponds
to one of the segments in the display.</P>
TFF (T Flip Flop)
</P>
This is a generic edge-triggered Toggle flip flop. When toggle is zero, the flip-flop is inactive. When
T is high, the flip-flop's output toggles its value upon a low-to-high clock transition.</P>
Toggle
The toggle switch \85 toggles between high and low with each click</P>
7400 Nand Gate
</P>
The Nand function is just the inverse of the And function; its output is zero (low) if all of the inputs
are one (high), and one otherwise. This is actually one-fourth of the chip.</P>
7401 Nand Gate with Open-Collector Output
</P>
The 7401 is functionally the same as the 7400, except the output is high-impedance when either input is
low. This gate is one fourth of the chip.</P>
7402 Nor Gate
</P>
The Nor function is the inverse of the Or function; its output is zero (external low) if one or more of
the inputs are one (high), and the output is one (external high) otherwise. This gate is one fourth of
the chip.</P>
7404 Inverter
</P>
The Inverter performs the logical function Y=NOT(A). This gate is one sixth of the chip.</P>
7405 Inverter with Open-Collector Output
This inverter is the same as the 7404, except that the output is a high impedance strength signal when
the input is low. The high impedance signal will appear as indeterminate when probed, and it should be
connected to a pull-up resistor to operate properly. This gate is one sixth of the chip.</P>
7406 Inverting buffer with Open-Collector Output
</P>
This inverter is the same as the 7404, except that the output is a high impedance strength signal when
the input is low, and the output can drive a substantial number of other gates. The output should be
connected to a pull-up resistor to operate properly. This gate is one sixth of the chip.</P>
7407 Non-inverting buffer with Open-Collector Output
</P>
This is a simple buffer whose output is a high impedance strength signal when the input is high. This
gate is one sixth of the chip.</P>
7408 And Gate
</P>
The And gate performs the logical function Y=A & B. The And function's output is one (high) if all
of the inputs are one, and zero otherwise. This gate is one fourth of the chip.</P>
7409 And Gate with Open Collector Output
</P>
This And gate performs the same as the 7408, except if any input is low, the output is a high-impedance
strength signal instead of one. This gate is one fourth of the chip.</P>
7410 Nand Gate (3 Inputs)
</P>
It's the same as the 7400, except all three inputs must be high for the output to be external low. This
gate is one-third of the chip. </P>
7411 And Gate (3 Input)
</P>
The 7411 performs the three input And function; i.e., all inputs must be high for the output to be high.
This gate is one-third of the chip.</P>
7412 Nand Gate w/ OC Output (3 Inputs)
</P>
The 7412 is the same as the 7410 except if all inputs are high, the output is a high-impedance strength
signal instead of one. This gate is one-third of the chip.</P>
7415 And Gate w/ OC Output (3 Inputs)
</P>
The 7415 is the same as the 7411 except if all inputs are high, the output is a high-impedance strength
signal instead of one. The output must be tied to a pull-up resistor for proper operation. This gate
is one-third of the chip. </P>
7420 Nand Gate (4 Inputs)
</P>
The 7420's output is high if at least one input is low, and its output is low if all inputs are high.
This gate is one-half of the chip.</P>
7421 And Gate (4 Inputs)
</P>
The 7421 performs the four input And function; i.e., all inputs must be high for the output to be high.
This gate is one-half of the chip.</P>
7422 Nand Gate w/Open Collector Output (4 Inputs)
</P>
The 7422 is the same as the 7420 except if all inputs are high, the output is a high-impedance strength
signal instead of one. This gate is one-half of the chip.</P>
7425 Nor Gate w/Strobe (4 Input, 5 w/strobe)
</P>
This is a 4-input nor gate with a twist. If the strobe is internal low the output will stay low. If the
strobe input (G) is logic high, then the output will be low if any of the inputs are logic high. This
unit is one-half of the chip. </P>
7426 Nand buffer with Open-Collector Output
</P>
This nand gate is the same as the 7400, except that the output is a high impedance strength signal when
the input is low, and the output can drive a substantial number of other gates. The output should be
connected to a pull-up resistor to operate properly. This gate is one fourth of the chip.</P>
7427 Nor Gate (3 Input)
</P>
The Nor gate's output is one (logic high) if one or more of the inputs are one (high), and zero (logic
low) otherwise. This gate is one-third of the chip.</P>
7428 Nor buffer (2 Input)
</P>
The Nor gate's output is one (logic high) if one or more of the inputs are one (high), and zero (logic
low) otherwise. This gate is one-third of the chip. The output can drive a substantial number of other
gates (Iol and Ioh are both large).</P>
7430 Nand Gate (8 Input)
</P>
The 7430's output is high if at least one input is low, and its output is low if all inputs are high.
This is the full chip.</P>
7432 Or Gate (2 Input)
</P>
This is one fourth of the chip. The Or gate's output is external high if one or more inputs are high,
and external low if all of the inputs are low.</P>
7433 Nor Buffer Gate with Open Collector Output(2 Input)
</P>
The 7433's output is high impedance strength if at least one input is low, and its output is low if all
inputs are high. The output should be connected to a pull-up resistor to operate properly. The output
delivers high Iol for greater fan-out. It performs the function Y = A + B.</P>
7437 Nand Buffer Gate (2 Input)
</P>
The 7437's output is high if at least one input is low, and its output is low if all inputs are high.
The output delivers high Iol and Ioh for greater fan-out. It performs the function Y = (A * B)'.</P>
7438 Nand Buffer Gate with Open Collector Output (2 Input)
</P>
The 7438's output is high impedance strength if at least one input is low, and its output is low if all
inputs are high. The output should be connected to a pull-up resistor to operate properly. The output
delivers high Iol for greater fan-out. It performs the function Y = (A * B)'.</P>
7442 BCD/Decimal Decoders
</P>
The 7442 contains eight inverters and ten, four input nand gates to convert BCD input into decimal output.
The outputs all remain off for the invalid input states greater than 9.</P>
7445 BCD/Decimal Decoder Buffer with Open Collector Complementary Output
</P>
The 7445 converts BCD input into decimal output. The outputs are inverted and open collector. The output
is also buffered allowing for greater driving capabilities.</P>
7447 BCD/ 7-Segment Decoder/Driver
The 7447 converts BCD input into output needed to drive the seven segment display. The output is buffered
allowing for greater driving capabilities.</P>
In order for the output to be the 7-segment output, the Lamp Test (LT) input must be high, and the blanking
input (BI) must be high or high-impedance. The ripple-blanking input (RBI) must be open or high if blanking
of a decimal zero is required.</P>
When a low level is applied to the BI, all segments' outputs go High.</P>
When RBI and inputs A,B,C,D are held low, and LT is high, all segment outputs go high and RBO goes low
also.</P>
When BI is held open or high, and low is applied to LT, all segment outputs are Low.</P>
7449 BCD/ 7-Segment Decoder/Driver
</P>
The 7449 converts BCD input into output needed to drive the seven segment display. The control input
(BI) must be open or high for the decoder to perform the decoding for functions 0 through 15. When low
is applied to BI, all segment outputs are low regardless of other input levels.</P>
7451 Dual 2-wide 2-input, 2-wide 3-input AND-OR-INVERT Gates
</P>
The 7451 contains two independent combinations of gates, each of which performs the logic AND-OR-INVERT
function.</P>
Y1 = ((A1 * B1 * C1) + (D1 * E1 * F1))'</P>
Y2 = ((A2 * B2) + (C2 * D2))'</P>
==7473 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary
Outputs==
</P>
CLEAR is independent of the CLOCK, and it's activated when it is Low as indicated by the inversion symbol.
The J and K data is processed on the falling edge of the clock pulse, as indicated by the inversion symbol
on the clock pin. If the J or K data change too close to the time that the CLOCK signal falls, a set-up
or hold time violation may occur.</P>
7474 D-Flip-Flop
</P>
PRESET and CLEAR are independent of the CLOCK, and they are activated when they are Low as indicated by
the inversion symbols. PRESET=0 causes Q=1, and CLEAR=0 causes Q=0. When set_bar=0 and reset_bar=0, the
outputs Q and Q_bar are both zero.</P>
When both set_bar and reset_bar are 1, D is transferred to the output Q on the positive going edge of
the clock. The 7474 is positive edge-triggered. </P>
7475 Quad D Latches with Complementary Outputs
</P>
When the enable input (G) is high, the data at D will be stored internally and presented at the output
Q. When G goes low, the data will remain at Q. These latches feature complementary outputs as well.
Each enable input controls two latches.</P>
7476 JK Flip-Flop
</P>
A low at the PRESET or CLEAR inputs sets the outputs regardless of the levels of the other inputs. With
the 7476 Standard library component, the next state is generated and latched internally while the clock
input is active high, and the outputs are released when the clock falls from high to low. The '76 components
from most other libraries are edge triggered, i.e. when the clock falls, the output is generated and released
in one step.</P>
If J = K = 0, then the outputs don't change. If J = K =1, the output toggles. If J=1 and K=0, then the
output will become 1, and if J = 0 and K = 1, then the output becomes 0.</P>
- Table shown is for 7476. 74LS76 will have negative transitions for clock signal in place of positive
pulses.</P>
7477 Quad D Latches
</P>
When the enable input (G) is high, the data at D will be stored internally and presented at the output
Q. When G goes low, the data will remain at Q. Each enable input controls two latches.</P>
7482 Adder (2-bit)
</P>
The adder calculates the sum of two binary 2-bit numbers. The result is placed in a 3-bit Output with
C2 (carry out) as the most significant bit, and *0 the least significant bit.</P>
7483A Adder
</P>
The adder calculates the sum of two binary 4-bit numbers. The result is placed in a 5-bit Output with
C4 (carry out) as the most significant bit, and *0 the least significant bit.</P>
7485 Comparator
</P>
The 7485 compares two four bit binary numbers. It has three outputs for P<Q, P=Q, and P>Q. If
P = Q, then the output which is active is selected as follows. </P>
If P = Q, and LT_in = 1 while EQ_in = GT_in = 0, then P<Q.</P>
If P = Q, and EQ_in = 1 while LT_in = GT_in = 0, then P=Q.</P>
If P = Q, and GT_in = 1 while EQ_in = LT_in = 0, then P>Q1.</P>
Words of greater length are compared by cascading comparators, i.e., the P<Q, P=Q, and P>Q inputs
of a less significant stage are connected to the corresponding inputs of the more significant stage.
The stage handling the least significant bits must have the P=Q input at high voltage and P<Q, P>Q
inputs at low voltage.</P>
7486 Exclusive Or
</P>
The Exclusive Or function generates an output value of one if exactly one of the inputs is one, and zero
otherwise.</P>
7489 Binary Rate Multiplier
</P>
The 7489 is a 4-bit binary rate multiplier that provides an output pulse rate which is the input clock
pulse rate multiplied by 1/16 times the binary input number. For example, if 7 is the binary input, then
there will be 7 output pulses for every 16 clock pulses.</P>
The INH IN input inhibits clock pulses, thus preventing any output pulses. The CLEAR and SET inputs are
used to set the binary count to the 0th or 15th pulse. The strobe input (ST) is used to inhibit or enable
the outputs. Also, if D is 1 and CLEAR is 1, then the output pulses for all 16 input pulses. This device
goes by the name 4089.</P>
7490 Decade Counter
</P>
This counter is capable of performing as a divide by two, divide by five, or divide by 10 counter. It
has gated zero reset, and gated set-to-nine inputs. Connect the output of the DIV2 block to the clock
input of the DIV5 block for a divide by 10 configuration. Notice that the counter is negative edge triggered.</P>
BCD COUNT SEQUENCE (Divide by 10 configuration)</P>
|
Count/ |
Qd |
Qc |
Qb |
Qa |
|
0/ |
L |
L |
L |
L |
|
1/ |
L |
L |
L |
H |
|
2/ |
L |
L |
H |
L |
|
3/ |
L |
L |
H |
H |
|
4/ |
L |
H |
L |
L |
|
5/ |
L |
H |
L |
H |
|
6/ |
L |
H |
H |
L |
|
7/ |
L |
H |
H |
H |
|
8/ |
H |
L |
L |
L |
|
9/ |
H |
L |
L |
H |
RESET/ COUNT TRUTH TABLE
|
R0(1) |
R0(2) |
R9(1) |
R9(2)/ |
Qd |
Qc |
Qb |
Qa |
|
H |
H |
L |
X/ |
L |
L |
L |
L |
|
H |
H |
X |
L/ |
L |
L |
L |
L |
|
X |
L |
X |
L/ |
COUNT |
|
|
|
|
L |
X |
L |
X/ |
COUNT |
|
|
|
|
X |
L |
L |
X/ |
COUNT |
|
|
|
7491 8-bit Shift Register
</P>
This device is an 8-bit shift register. The two lowest inputs are gated to form the serial input to the
shift register. The clock input is positive edge triggered. The current serial input appears at the
output after 8 of these clock triggers.</P>
7492 Divide by 12 Counter
</P>
This counter is capable of performing as a divide by two, divide by three, divide by 6, or divide by 12
counter. It has gated zero reset. Connect the output of the DIV2 block to the clock input of the DIV3
block for a divide by 12 configuration. Notice that the counter is negative edge triggered.</P>
7493 Binary Counter
</P>
This counter is capable of performing as a divide by two, divide by three, divide by 8, or divide by 16
counter. It has gated zero reset. Connect the output of the DIV2 block to the clock input of the DIV8
block for a divide by 16 configuration. Notice that the counter is negative edge triggered.</P>
74109 J-K' Flip-Flop
</P>
This flip flop works just like the 74LS76, except that the K input is inverted. PRESET and CLEAR are
independent of the CLOCK, and they are activated when they are Low as indicated by the inversion symbols.
PRESET=0 causes Q=1, and CLEAR=0 causes Q=0. The triangle before the clock (c1) indicates that the 74109
is positive edge-triggered. </P>
74112 J-K Flip-Flop (Clock Inverted)
</P>
This flip flop works just like the 74LS76, except that the clock input is inverted. PRESET and CLEAR
are independent of the CLOCK, and they are activated when they are Low as indicated by the inversion symbols.
PRESET=0 causes Q=1, and CLEAR=0 causes Q=0. The triangle before the clock (c1) indicates that the 74112
is negative edge-triggered, i.e., when the clock input falls from Hi to Low, the J and K inputs are latched
and the appropriate outputs appear shortly after.</P>
==74113 Negative-Edge-Triggered Master-Slave JK Flip-Flop with Preset and Complementary
Outputs==
</P>
This flip flop works just like the 74LS76, except that the CLOCK input is inverted. PRESET is independent
of the CLOCK, and is active when its logic level is Low as indicated by the inversion symbols. PRESET=0
causes Q=1. The inversion symbol before the clock (c1) indicates that the 74113 is negative edge-triggered.
</P>
74123 Retriggerable One-Shot with Clear and Complementary Outputs
</P>
The 74123 is a dual retriggerable monostable multivibrator capable of generating output pulses from a
few nano-seconds to extremely long duration up to 100% duty cycle. It has three inputs permitting the
choice of either leading edge or trailing edge triggering. Pin A is an active low transition trigger,
and pin B is active-high transition trigger. The clear (CLR) terminates the output pulse when it is
activated. CLR also serves as a trigger input when it is pulsed with a low-level pulse transition.</P>
In the real world, the basic output pulse width is determined by selection of values for Rx and Cx. In
the program, the user directly specifies the basic pulse width, tw (in nanoseconds), in the dialog box
for the '123. Once triggered, the basic pulse width may be extended by retriggering the inputs A and
B. The pulse width may be reduced by use of the active low or CLEAR input.</P>
74126 Quadruple Bus Buffers W/ 3-State Outputs
</P>
The 74126 has four tri-state buffers which can be used to drive busses. When G is high, the output (Y)
takes the value of the input A. When G is 0, the output acts as a no-connection (high impedance).</P>
74136 Exclusive Or Gate with Open-Collector Output
</P>
The 74136 gate is one-fourth of the chip. When exactly one input is high, the output (Y) becomes high.
Otherwise, the output acts as a no-connection (high impedance).</P>
74138 3-Line to 8-Line Decoder/Demultiplexer
</P>
The 74138 decodes a three bit binary number into one of eight outputs.</P>
If the device is enabled, the decoded output line will be external low. When G1=1, G2A'=0, and G2B'=0,
the device is enabled. Otherwise, the outputs are all external high. The device can be used as a demultiplexer
by using G1 as a fourth data input.</P>
74138 3-Line to 8-Line Decoder/Demultiplexer
</P>
The 74138 decodes a three bit binary number into one of eight outputs.</P>
If the device is enabled, the decoded output line will be external low. When G1=1, G2A'=0, and G2B'=0,
the device is enabled. Otherwise, the outputs are all external high. The device can be used as a demultiplexer
by using G1 as a fourth data input.</P>
74139 Dual 2-Line to 4-Line Decoder/Demultiplexer
</P>
Each cell of the 74139 decodes a two bit binary number into one of four outputs. If the cell is enabled,
the decoded output line will be external low. Otherwise, the outputs are all external high. The device
can be used as a demultiplexer by using G as a third data input.</P>
74148 Priority Encoder
</P>
The 74148 detects the low level of the highest order among the eight inputs, and outputs the corresponding
signal position in binary code on the signal lines A0 through A2. Outputs EO and GS are the outputs to
indicate the operational mode of the encoder and are used when the number of bits is to be increased by
cascading. When EI is set to the high level, the encode operation is inhibited by making all the outputs
high.</P>
74151 1 of 8 Multiplexer
</P>
One of eight data input signals (D0 - D7) is selected by decoding the three-bit select input (A-C). The
selected data appears at the output Y and the inverting output W.</P>
The strobe input (G_bar) must be at a low logic level to enable the device. A high level at the strobe
forces the W output high and Y low.</P>
74153 Dual 1 of 4 Multiplexer
</P>
The select inputs (A & B) form a 2-bit number used to select one of four inputs from each of the two
1-of-4 multiplexers. If the strobe input (G_bar) is at a high logic level, disabling the device, the
output will be fixed at a low level.</P>
74157 Quadruple 1 of 2 Multiplexers/Data Selectors
</P>
A 4-bit word is selected from either the A inputs or the B inputs and routed through to the outputs.
The A inputs are selected if the select line is low, and the B inputs are routed through if the select
line is high. If G is High, disabling the device, the outputs will all be fixed at 0.</P>
74161 4-Bit Binary Counter
</P>
This is a synchronous mod-16 binary counter with the following capabilities:</P>
a)
parallel loading controlled by the clock when the mode is zero</P>
b)
common clear by bringing reset to zero</P>
c)
ripple-carry output when count=15</P>
d)
count-up on the positive clock edge provided that count_enable is one, and
the mode is 1.</P>
- The model for the 74161 is activated by an edge-trigger. In reality, the standard library 74161 is
triggered by a low level at the clock input, but most implementations of the '161 are edge triggered like
the model.</P>
74163 4-Bit Binary Counter
</P>
The 74163 is functionally the same as the 74161, except that the reset terminal (5CT=0) is only active
when the clock rises.</P>
- The model for the 74163 is activated by an edge-trigger. In reality, the standard library 74163 is
triggered by a low level at the clock input, but most implementations of the '163 are edge triggered like
the model.</P>
74169 Synchronous 4-bit Up/Down Binary Counter
</P>
The counter can operate in three modes, parallel load, count up, and count down. When either of the enable
lines (ENT and ENP) are high, the clock is inhibited and the device holds its present value. When the
load input is zero and the enable lines are low, the inputs are loaded upon a positive clock transition.
The device counts when the load input is one, the enable lines are low, and the clock makes a positive
transition. The direction of the count is determined by the up/down select line. When U/D_bar is low,
it counts down. The RCO output is a ripple carry output. It goes low when the counter is going down
and the value is zero, and when the counter direction is up and the value is fifteen.</P>
74175 Quad D-Flip-Flops
</P>
This 4-bit register is made up of 4 D-flip-flops with a common clock and a common clear. When the clock
goes from 0-to-1, Q takes the value of D (as long as CLR' is 1). CLR' is an asynchronous input. When
it's zero, Q is zero, regardless of everything else. There is only one of these registers on the 74175.</P>
74181 Arithmetic Logic Unit
</P>
The 74181 performs 32 binary arithmetic/logic functions on two four bit words according to the following
table. The propagate and generate outputs are for use in conjunction with carry look-ahead generators.</P>
When the mode control input (M) is low, the carry-in input is enabled for arithmetic functions. When
M is high, the carry-in input is disabled for the logic functions.</P>
</P>
|
Selection </P> | <TD WIDTH="130">
M=H</P></TD><TD WIDTH="175">
M=L</P></TD>
<TR><TD WIDTH="95">
0
</TD><TD WIDTH="130">
F=A'
</TD><TD WIDTH="175">
F = A minus 1
</TD></TR>
<TR><TD WIDTH="95">
1
</TD><TD WIDTH="130">
F=(AB)'
</TD><TD WIDTH="175">
F= (AB) minus 1
</TD></TR>
<TR><TD WIDTH="95">
2
</TD><TD WIDTH="130">
F=A'+B
</TD><TD WIDTH="175">
F=(AB') minus 1
</TD></TR>
<TR><TD WIDTH="95">
3
</TD><TD WIDTH="130">
F=1
</TD><TD WIDTH="175">
F=minus 1 (2'S comp)
</TD></TR>
<TR><TD WIDTH="95">
4
</TD><TD WIDTH="130">
F= (A+B)'
</TD><TD WIDTH="175">
F = A plus (A+B')
</TD></TR>
<TR><TD WIDTH="95">
5
</TD><TD WIDTH="130">
F=B'
</TD><TD WIDTH="175">
F=(AB) plus (A+B')
</TD></TR>
<TR><TD WIDTH="95">
6
</TD><TD WIDTH="130">
F={A XOR B)'
</TD><TD WIDTH="175">
F=A minus B minus 1
</TD></TR>
<TR><TD WIDTH="95">
7
</TD><TD WIDTH="130">
F=A + B'
</TD><TD WIDTH="175">
F=A + B'
</TD></TR>
<TR><TD WIDTH="95">
8
</TD><TD WIDTH="130">
F= A'B
</TD><TD WIDTH="175">
F = A plus (A+B)
</TD></TR>
<TR><TD WIDTH="95">
9
</TD><TD WIDTH="130">
F = A XOR B
</TD><TD WIDTH="175">
F = A plus B
</TD></TR>
<TR><TD WIDTH="95">
10
</TD><TD WIDTH="130">
F=B
</TD><TD WIDTH="175">
F = AB' plus (A+B)
</TD></TR>
<TR><TD WIDTH="95">
11
</TD><TD WIDTH="130">
F = A + B
</TD><TD WIDTH="175">
F= (A + B)
</TD></TR>
<TR><TD WIDTH="95">
12
</TD><TD WIDTH="130">
F=0
</TD><TD WIDTH="175">
F= A plus A
</TD></TR>
<TR><TD WIDTH="95">
13
</TD><TD WIDTH="130">
F = AB'
</TD><TD WIDTH="175">
F = AB plus A
</TD></TR>
<TR><TD WIDTH="95">
14
</TD><TD WIDTH="130">
F = AB
</TD><TD WIDTH="175">
F = AB' plus A
</TD></TR>
<TR><TD WIDTH="95">
15
</TD><TD WIDTH="130">
F = A
</TD><TD WIDTH="175">
F = A
</TD></TR></TABLE>
74182 Look-Ahead Carry Generator
</P>
This is a high-speed device capable of anticipating a carry across a group of adders. They are used to
speed up addition of many bits, and they may be cascaded.</P>
The logic equations for the 74182 are</P>
Cn+x = G0 + P0Cn
Cn+y = G1 + P1(Cn+x)
Cn+z = G2 + P2(Cn+y)
G = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0
P = P3*P2*P1*P0
74192 Synchronous 4-bit BCD Up/Down Counter with Dual Clock
</P>
The count output is triggered by a low-to-high level transition of either clock input. The counting direction
is determined by which clock input is pulsed while the other is high. The counter can be loaded with
any value by entering the value while the load input (C3) is low. A clear input is provided which forces
the output to zero when a high level is applied. Both borrow and carry outputs are provided to facilitate
cascading. The borrow output is active when counting down and the output is zero, and the carry output
is active when counting up and the output is 9. To cascade them, feed the borrow and carry outputs to
the count-down and count-up inputs of the succeeding counter.</P>
74193 Synchronous 4-bit Binary Up/Down Counter with Dual Clock
</P>
The count output is triggered by a low-to-high level transition of either clock input. The counting direction
is determined by which clock input is pulsed while the other is high. The counter can be loaded with
any value by entering the value while the load input (C3) is low. A clear input is provided which forces
the output to zero when a high level is applied. Both borrow and carry outputs are provided to facilitate
cascading. The borrow output is active when counting down and the output is zero, and the carry output
is active when counting up and the output is 15. To cascade them, feed the borrow and carry outputs to
the count-down and count-up inputs of the succeeding counter.</P>
74194 4-bit Bi-directional Universal Shift Register
</P>
This multifunctional register features parallel outputs, right and left shift serial inputs, operating
mode control inputs, and an overriding clear line. Synchronous parallel loading is accomplished by setting
both S0 and S1 to one. Upon a positive clock transition, the inputs are loaded into the outputs. </P>
When S0 is zero and S1 is one, shift right is accomplished synchronously. SR SER is fed into QA. When
S0 is one and S1 is zero, shift left is accomplished synchronously. SL SER is fed into QD. Clocking
is inhibited when S0 and S1 are both zero.</P>
74244 Octal Buffer And Line Driver with 3-State output
</P>
This device features high fan out and three-state outputs. Transmission can only occur in one direction.</P>
74245 Octal Bus Transceivers w/ 3-St. Output
</P>
This device allows data transmission in either direction, depending on the logic level of the direction
control input. The enable input must be external logic low, or else the buses are effectively isolated
from each other.</P>
74266 Exclusive Nor with Open Collector Output
</P>
The Exclusive Nor function generates an external output value of zero if exactly one of the inputs is
one, and one otherwise.</P>
74279 R'-S' Latches
</P>
Each cell works as follows. If s'=0 and r'=1, the latch is set (i.e. Q=1). If s'=1 and r'=0, the latch
is reset (i.e. Q=0). If both inputs are 1, then the outputs don't change from the previous state. If
both inputs are 0, then the result is unknown. In the three input cells, the two s' inputs must both
be external logic low in order to set the latch.</P>
74280 9 Bit Odd/Even Parity Generator
</P>
The top output is external logic high if an even number of inputs are logic high, and the bottom output
is external logic high if an odd number of inputs are logic high. </P>
74373 Octal D-Type Transparent Latches
</P>
The register features three-state outputs which makes it attractive for implementing buffer registers,
I/O ports, and bi-directional bus drivers. When the clock is high, the data at the input is transferred
to the output.</P>
74374 Octal D-Type Transparent Flip-Flops
</P>
The register features three-state outputs which makes it attractive for implementing buffer registers,
I/O ports, and bi-directional bus drivers. On the positive clock transition, the data at the input is
transferred to the output. The EN input makes the outputs high impedance when it is external low.</P>
74381 Arithmetic Logic Unit
</P>
The 74LS381A performs eight binary arithmetic/logic functions on two four bit words according to the following
table. The propagate and generate outputs are for use in conjunction with carry look-ahead generators.</P>
74393 4-Bit Binary Counter
</P>
This is one-half of the chip. On each rise of the clock signal, the output is incremented. The reset
signal sets the outputs to zero independently of the clock.</P>
74521 Eight bit Comparator
</P>
This eight bit comparator is cascadable since it has an A=B input. If the numbers being compared are
not more than 8-bits wide, then set the A=B input to external low.</P>
74541 Octal Buffer with 3-State Outputs
</P>
G1' and G2' must both be external logic low for the device to be enabled, otherwise the outputs will be
effectively disconnected, i.e. at high impedance strength.</P>
74646 Octal Bus Transceiver and Register
</P>
This device is a bus transceiver with three-state outputs, D flip flops, and control circuitry laid out
for multiplexed transmission of data directly to and from the internal registers.</P>
G' controls whether the device is effectively isolated from the rest of the circuit. When G' is logic
high, all pins generate high-impedance outputs, however, data may still be input to the internal register.
DIR controls the direction of output flow. </P>
When DIR is high, the B data lines generate output data. The data comes from the internal A registers
if SAB is high, and the data flows straight from the A inputs if SAB is low. When DIR is low, the A data
lines generate output data. The data comes from the internal B registers if SBA is high, and the data
flows straight from the B inputs if SBA is low.</P>
At any time, data may be stored into the internal registers. When CAB rises, data on the A bus are stored
into the internal A register. When CBA rises, data on the B bus are stored into the internal B register.</P>
