Changes

RF.Spice A/D Glossary

8,868 bytes added, 16:14, 7 October 2024
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==D Flip-Flop==
 
[[File:G52.png]]
 
The digital D-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). In addition, there are asynchronous set and reset signals, which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! D !! Q !! Notes
|-
|[[File:NonRising.png]] || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Data Transfer
|-
|[[File:Rising.png]] || 1 || 1 || Data Transfer
|-
|}
</td>
</tr>
</table>
 
==D Latch==
 
[[File:G54.png]]
 
The digital D-type latch is a one-bit, level-sensitive storage element which outputs the value on the data (D) line whenever the enable (EN) input line is 1 (high). The value on the data line is stored, i.e., held on the output (Q) line whenever the enable (EN) line is 0 (low). In addition, there are set and reset signals, which are independent of the enable line. When SET = RESET = 0, the data on the D line is transferred to the output Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! EN !! D !! Q !! Notes
|-
|0 || X || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 0 || Reset
|-
|1 || 1 || 1 || Set
|-
|}
</td>
</tr>
</table>
== DC Bias Sources Vcc, Vee, Vdd, Vss ==
|-
|fraction||smoothing fraction/absolute value switch||true
|-
|}
 
==Ideal Buffer Block==
 
[[File:GL40.png]]
 
This model is an ideal buffer block with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|gain||gain||-||1.0||
|-
|}
where v<sub>P</sub> is the primary voltage, v<sub>S1</sub> is measured between the top secondary pin S1 and the center tap pin, and v<sub>S2</sub> is measured between the center tap pin and the bottom secondary pin S2. The red dots show the polarity of the windings on each side. This model has one parameter: ratio = n = N<sub>P</sub>/N<sub>S1</sub> = N<sub>P</sub>/N<sub>S2</sub>, which represents the primary-to-secondary (half-winding) turns ratio.
 
==Ideal Comparator Block==
 
[[File:GL51.png]]
 
This block is an ideal two-signal voltage comparator with a default unity gain. It has a binary output that takes a value of 0V if v<sub>pos</sub> < v<sub>neg</sub> and takes a value of 1V if v<sub>pos</sub> > v<sub>neg</sub>. If v<sub>pos</sub> = v<sub>neg</sub>, the output voltage is 0.5V.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||comparator gain||-||1.0||
|-
|}
 
==Ideal Delay Block==
 
[[File:GL44.png]]
 
This model is an ideal signal delay block based on an ideal delay line model.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|delay||time delay||sec||1u||
|-
|}
==Ideal Diode==
None
 
==Ideal Full-Wave Rectifier Block==
 
[[File:GL47.png]]
 
This block rectifies an input signal at both positive and negative cycles with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||rectifier gain||-||1.0||
|-
|}
 
==Ideal Gyrator Block==
 
[[File:GL48.png]]
 
An ideal gyrator is a linear two-port device which couples the current on one port to the voltage on the other and vice versa. The instantaneous voltages and currents instantaneous are related by:
 
:<math>v_{out}(t) = R \cdot i_{in}(t) </math>
 
:<math>v_{in}(t) = - R \cdot i_{out}(t) </math>
 
The ideal gyrator acts as an impedance inverter.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r||gyration resistance||&Omega;||1.0||
|-
|}
 
==Ideal Half-Wave Rectifier Block==
 
[[File:GL46.png]]
 
This block rectifies an input signal at positive cycles with a default unity gain. Its output at negative cycles is zero.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||rectifier gain||-||1.0||
|-
|}
==Ideal Operational Amplifier (Op-Amp)==
|-
|A||open loop gain||-||50,000||
|-
|}
 
==Ideal Phase Shifter Block==
 
[[File:GL45.png]]
 
This model is an ideal signal phase shifter block based on an ideal transmission line segment model. It is frequency-dependent and the signal phase shift is accurate only around the specified center frequency.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|phi||phase shift||deg||90||must be positive
|-
|fo||center frequency||Hz||1Meg||
|-
|}
 
==Ideal Polarity Detector Block==
 
[[File:GL66.png]]
 
This 3-pin device measures the difference signal &Delta;v = v<sub>pos</sub> - v<sub>neg</sub> and produces a binary output &plusmn;A according to the sign of &Delta;v, where A is a user defined amplitude.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|MaxVal||output amplitude||V||1||
|-
|}
 
==Ideal Splitter Block==
 
[[File:GL41.png]]
 
This model is an ideal signal splitter block with a default one-half split ratio. It splits the input signal by a ratio of k:(1-k).
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|k||split ratio||-||0.5||
|-
|}
where v<sub>P</sub>, i<sub>P</sub>, N<sub>P</sub> are the primary voltage, current and number of turns, respectively, and v<sub>S</sub>, i<sub>S</sub>, N<sub>S</sub> are the secondary voltage, current and number of turns, respectively. The red dots show the polarity of the windings on each side. This model has one parameter: ratio = n = N<sub>P</sub>/N<sub>S</sub>, which represents the primary-to-secondary turns ratio. Note that the ideal transformer model is defined based on controlled sources and does not involve any magnetic physical parameters as opposed to mutual inductors or ferrite core transformer.
 
== Impulse Generator ==
 
[[File:GL19.png]]
 
This is a voltage source that generates a periodic impulse train with oscillating between zero and a user defined maximum voltage level.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|T||impulse period||sec||1u||required
|-
|duty_cycle||impulse duty cycle||-||0.01||required
|-
|max_val||maximum output voltage level||V||1||
|-
|delay||delay time||sec||0||
|-
|}
==Inductance Meter==
|-
|cjo||diode junction capacitance||F||1n||
|-
|}
 
== Integer Modulo Block ==
 
[[File:GL58.png]]
 
This 3-pin device requires a voltage with an integer value on its second input pin. It produces a voltage equal to v<sub>in1</sub> % v<sub>in2</sub> and sends it to the output with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|}
 
==Integrator Block==
 
[[File:G32.png]]
 
The Integrator Gain and input offset parameters are also included to allow for tailoring of the required
signa. Output upper and lower limits are also included to prevent convergence errors resulting from excessively
large output values. Note that these limits specify integrator behavior similar to that found in an operational
amplifier-based integration stage, in that once a limit is reached, additional storage does not occur.
Thus the input of a negative value to an integrator which is currently driving at the out_upper_limit
level will immediately cause a drop in the output, regardless of how long the integrator was previously
summing positive inputs. The incremental value of output below the output_upper_limit and above the output_lower_limit
at which smoothing begins is specified via the limit_range parameter. In AC analysis, the value returned
is equal to the gain divided by the radian frequency of analysis.
 
Note that truncation error checking is included in the \93int\94 block. This should provide for a more accurate
simulation for the time integration function, since the model will inherently request smaller time increments
between simulation points if truncation errors would otherwise be excessive.
 
Model Identifier: int
 
Netlist Format:
 
A&lt;device_name&gt; &lt;in_pin&gt; &lt;out_pin&gt; &lt;model_name&gt;
 
.model &lt;model_name&gt; int out_lower_limit = &lt;value&gt; out_upper_limit = &lt;value&gt; {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 1 2 integrator_block
 
.model integrator_block int out_lower_limit = -1t out_upper_limit = 1t
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|in_offset||output offset||V||0.0||
|-
|out_lower_limit||output lower limit||V||-1t||required
|-
|out_upper_limit||output upper limit||V||1t||required
|-
|limit_range||upper and lower limit smoothing range||-||1.0e-6||
|-
|out_ic||output initial condition||V||0.0||
|-
|}
This device is an interactive switch that can be closed or opened either directly from the Schematic Editor by clicking on its symbol or from the Instrument Panel.
 
==Interdigital Capacitor==
[[File:G97.png]]
 
This is a four-pin, two-port device that models a planar interdigital capacitor.
 
Model Identifier: interdigital
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||finger strip width||mm||0.1||
|-
|s||finger strip spacing||mm||0.1||
|-
|N||number of fingers||-||5||
|-
|l||capacitor length||mm||1.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|}
 
==Inverted Microstrip Line==
[[File:GK62.png]]
 
This is a four-pin, two-port device that models an inverted microstrip line segment on a single-layer dielectric slab/substrate placed at a specified height above a ground plane.
 
Model Identifier: microstrip-inverted
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||microstrip width||mm||4.8||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|b||microstrip height above ground||mm||1.6||
|-
|len||microstrip length||m||10||
|-
|}
==Junction Field Effect Transistor (JFET)==
Asabet
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