Changes

RF.Spice A/D Glossary

54,430 bytes removed, 16:04, 7 October 2024
|-
|in_high||minimum 1-valued analog input||V||0.9||required
|-
|}
 
== 4-Bit A/D Converter Block ==
 
[[File:GK21.png]]
 
This is a 5-pin mixed-signal device with an analog input and 4 digital outputs. Based on the specified maximum input voltage level, a total of 16 discrete voltage levels are established. The block fits the input analog voltage between two of these 16 discrete levels and outputs the 4-bit binary equivalent to 4 digital pins B0-B3 representing the LSB and MSB, respectively.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|max_val||maximum input voltage||V||5||
|-
|}
|-
|out_high||analog output for 1 digital input||V||1||required
|-
|}
 
== 4-Bit D/A Converter Block ==
 
[[File:GK22.png]]
 
This is a 5-pin mixed-signal device with 4 digital inputs and an analog output. Based on the specified low and high output voltage levels, a total of 16 discrete voltage levels are established. The block converts the input 4-bit word (B0-B3 representing the LSB and MSB, respectively) to the corresponding discrete voltage level and outputs it as an analog voltage signal.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|out_low||output low voltage level||V||0||
|-
|out_high||output high voltage level||V||5||
|-
|}
 
== 4-Bit Signal Digitizer Block ==
 
[[File:GK15.png]]
 
This is a 6-pin mixed-signal device with an analog input, a digital clock and 4 digital outputs. It samples its analog input signal at the period of the supplied digital clock. The digitized version of the input signal is sent out to 4 digital outputs B0-B3 representing the LSB and MSB, respectively.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||Ω||10G||
|-
|max_val||maximum input voltage||V||5||
|-
|}
 
==50-Ohm Load==
[[File:GK70.png]]
 
This is a simple 50Ω resistive load, which can also be accessed by the keyboard shortcut {{key|Alt+5}}.
 
== 8-Bit A/D Converter Block ==
 
[[File:GK23.png]]
 
This is a 9-pin mixed-signal device with an analog input and 8 digital outputs. Based on the specified maximum input voltage level, a total of 256 discrete voltage levels are established. The block fits the input analog voltage between two of these 256 discrete levels and outputs the 8-bit binary equivalent to 8 digital pins B0-B7 representing the LSB and MSB, respectively.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|max_val||maximum input voltage||V||5||
|-
|}
 
== 8-Bit D/A Converter Block ==
 
[[File:GK24.png]]
 
This is a 9-pin mixed-signal device with 8 digital inputs and an analog output. Based on the specified low and high output voltage levels, a total of 256 discrete voltage levels are established. The block converts the input 8-bit word (B0-B7 representing the LSB and MSB, respectively) to the corresponding discrete voltage level and outputs it as an analog voltage signal.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|out_low||output low voltage level||V||0||
|-
|out_high||output high voltage level||V||5||
|-
|}
|-
|FS||signal frequency ||Hz||1||required
|-
|}
 
== Amplitude Modulator Block==
 
[[File:GL87.png]]
 
This device takes an input signal and generates an AM modulated output signal of a specified carrier frequency with a specified modulation index.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||Ω||1G||
|-
|r_out||output resistance||Ω||1u||
|-
|m||modulation index||-||0.5||
|-
|fc||carrier frequency||Hz||1Meg||
|-
|ac||carrier peak amplitude||V||1||
|-
|}
 
== Amplitude Shift-Keying Modulator Block==
 
[[File:GL91.png]]
 
This device takes a digital input like a binary sequence and generates an ASK modulated output signal with two specified carrier amplitude levels.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_out||output resistance||Ω||1u||
|-
|fc||carrier frequency||Hz||1Meg||
|-
|ac_lo||low carrier peak amplitude||V||0.0||
|-
|ac_hi||high carrier peak amplitude||V||1.0||
|-
|}
|-|-
|out_high||high output voltage level||V||5||
|-
|}
 
== Analog Differentiator Block ==
 
[[File:GK32.png]]
 
This device outputs the derivative of its input signal. It is a native [[RF.Spice A/D]] block and different from the XSPICE Differentiator Block, which is a more extensive model.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|offset||offset voltage||V||0||
|-
|fmax||maximum signal frequency||Hz||1Meg||
|-
|}
 
== Analog integrator Block ==
 
[[File:GK33.png]]
 
This device outputs the integral of its input signal assuming zero initial conditions. It is a native [[RF.Spice A/D]] block and different from the XSPICE Integrator Block, which is a more extensive model.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|offset||offset voltage||V||0||
|-
|fmax||maximum signal frequency||Hz||1Meg||
|-
|}
 
== Analog One-Half Frequency Divider Block==
 
[[File:GL78.png]]
 
This device takes a harmonic input signal and generates a harmonic output signal with a frequency one half lower and a user specified amplitude.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||Ω||1G||
|-
|r_out||output resistance||Ω||1u||
|-
|max_val||output amplitude||V||1.0||
|-
|}
 
== Analog Phase-Locked Loop Block==
 
[[File:GL86.png]]
 
This 5-pin device is a parameterized model of an analog phase-locked loop. It provides two phase-locked output signals with square wave and triangular wave waveforms. The outputs of the lowpass filter and phase detector are also accessible via the designated pins.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||Ω||1G||
|-
|r_out||output resistance||Ω||1u||
|-
|K_d||voltage conversion factor of phase detector||V/rad||1.0||
|-
|K_f||frequency conversion factor of VCO||Hz/V||1k||
|-
|V_sq||square wave output peak amplitude||V||1||
|-
|V_tri||triangular wave output peak amplitude||V||1||
|-
|VT||VCO input dynamic range||V||1||
|-
|r_time||VCO timing resistor||Ω||12k||
|-
|c_time||VCO timing capacitor||F||10n||
|-
|fo||VCO free-running frequency||Hz||1k||
|-
|r_lpf||lowpass filter resistor||Ω||10k||
|-
|c_lpf||lowpass filter capacitor||F||100n||
|-
|}
|-
|Tmax||maximum signal duration||sec||1e6||required
|-
|}
 
== Arithmetic Mean Block ==
 
[[File:GL56.png]]
 
This 3-pin device sends the arithmetic mean or average of its two inputs to the output with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|}
 
==Attenuator: Pi-Type==
[[File:G75.png]]
 
This is a four-pin, two-port device that models a resistive power attenuator with the "Pi" configuration. The characteristic impedances of the input and output transmission lines can be different. The K-parameter is the power attenuation ratio from the input to the output.
 
Model Identifier: attenuator Pi
'''Bold text'''
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Zo1||input line characteristic impedance||Ohms||50.0||
|-
|Zo2||output line characteristic impedance||Ohms||50.0||
|-
|K||input/output power ratio||-||1.0||
|-
|}
 
==Attenuator: T-Type==
[[File:G74.png]]
 
This is a four-pin, two-port device that models a resistive power attenuator with the "T" configuration. The characteristic impedances of the input and output [[Transmission Lines|transmission lines]] can be different. The K-parameter is the power attenuation ratio from the input to the output.
 
Model Identifier: attenuator T
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Zo1||input line characteristic impedance||Ohms||50.0||
|-
|Zo2||output line characteristic impedance||Ohms||50.0||
|-
|K||input/output power ratio||-||1.0||
|-
|}
|-
|k||coefficient of coupling||-||1.0||
|-
|}
 
==Bias Tee==
[[File:G83.png]]
 
This is a six-pin, three-port device that models a passive RF bias tee. The two RF and DC inputs mix into the output (RF+DC) port.
 
Model Identifier: bias-tee
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|L||inductance||nH||100.0||
|-
|C||capacitance||nF||100.0||
|-
|}
|-
|TNOM||parameter measurement temperature||deg. C||27||50
|-
|}
 
==Bond Wire Above Ground==
[[File:GK55.png]]
 
This is a two-pin, one-port device that models a bond wire including the ground effect.
 
Model Identifier: BondWire-Free
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r||wire radius||mm||0.1||
|-
|l||pad spacing||mm||1.0||
|-
|h||height above ground||mm||1.0||
|-
|sigma||wire conductivity||S/m||1e8||
|-
|}
 
==Bond Wire (Free-Space)==
[[File:GK54.png]]
 
This is a two-pin, one-port device that models a bond wire with no ground effect.
 
Model Identifier: BondWire-Free
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r||wire radius||mm||0.1||
|-
|l||pad spacing||mm||1.0||
|-
|sigma||wire conductivity||S/m||1e8||
|-
|}
 
==Branchline Hybrid Coupler==
[[File:G81.png]]
 
This is an eight-pin, four-port device that models a branchline quadrature hybrid coupler. If Port 1 acts as an input port, the output power is equally split between Ports 2 and 3. Port 2 has 90° phase shift with respect to the input, while Port 3 is in-phase with respect to the input. Port 4 acts as an isolated port. Since the branchline hybrid has a symmetric structure, any port can serve as the input port. You have to specify the center frequency of the device in GHz.
 
Model Identifier: branchline
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Z0||line characteristic impedance||Ohms||50.0||
|-
|eeff||effective permittivity||-||1.0||
|-
|fc||center frequency||GHz||1.0||
|-
|len||port line segment length||mm||10.0||
|-
|}
|-
|length||core length||m||0.01||
|-
|}
 
==Chip Resistor==
[[File:G94.png]]
 
This is a four-pin, two-port device that models a semiconductor chip resistor. The resistor is made of a thin film deposited between two Ohmic pads on a dielectric substrate.
 
Model Identifier: chip resistor
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||thin film width||mm||1.0||
|-
|l||thin film length||mm||2.0||
|-
|d||thin film thickness||mm||0.1||
|-
|sigma||thin film conductivity||S/m||5.0||
|-
|wp||Ohmic pad width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|}
 
== Clocked Sample-and-Hold Block ==
 
[[File:GK12.png]]
 
This device samples its input signal at a specified sampling period and holds the values of each sample during each clock cycle. The output signal is a quantized version of the input signal.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|duty_cycle||sampling pulse duty cycle||-||0.1||
|-
|Tmax||signal period or maximum duration||sec||10||
|-
|}
 
==Coaxial Line==
[[File:G91.png]]
 
This is a four-pin, two-port device that models a coaxial line segment with a dielectric core.
 
Model Identifier: coaxial-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||inner conductor radius||mm||5.0||
|-
|r_out||outer conductor radius||mm||10.0||
|-
|er||core dielectric relative permittivity||-||2.2||
|-
|len||coaxial line length||mm||10.0||
|-
|sigma||metal conductivity||S/m||1e10||
|-
|tand||core dielectric loss tangent||-||0||
|-
|}
 
==Coaxial Step in Inner Conductor==
[[File:G112.png]]
 
This is a four-pin, two-port device that models a step in inner conductor radius between two coaxial lines of equal outer conductor radius with a dielectric core.
 
Model Identifier: coaxial-innerstep
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in1||smaller inner conductor radius||mm||2.0||
|-
|r_in2||larger inner conductor radius||mm||4.0||
|-
|r_out||outer conductor radius||mm||5.0||
|-
|er||core dielectric relative permittivity||-||2.2||
|-
|}
 
==Coaxial Step in Outer Conductor==
[[File:G113.png]]
 
This is a four-pin, two-port device that models a step in outer conductor radius between two coaxial lines of equal inner conductor radius with a dielectric core.
 
Model Identifier: coaxial-outerstep
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||inner conductor radius||mm||2.0||
|-
|r_out1||smaller outer conductor radius||mm||4.0||
|-
|r_out2||larger outer conductor radius||mm||6.0||
|-
|er||core dielectric relative permittivity||-||2.2||
|-
|}
 
== Comparator with Hysteresis ==
 
[[File:GL52.png]]
 
This device is a 3-pin two-signal voltage comparator block with hysteresis effect. If the output voltage is at its low level and you increase &Delta;v = (v<sub>pos</sub> - v<sub>neg</sub>), the output switches to the high level as soon as &Delta;v > V_hys. If the output voltage is at its high level and you decrease &Delta;v = (v<sub>pos</sub> - v<sub>neg</sub>), the output switches to the low level as soon as &Delta;v < -V_hys.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|V_hi||high output voltage level||V||5||
|-
|V_lo||high output voltage level||v||100m||
|-
|V_hys||hysteresis voltage width||V||50m||
|-
|}
 
==Complex Impedance==
[[File:G73.png]]
 
This is a two-pin, one-port device that models a generic impedance with both real and imaginary parts. It can be used in place of a one-port device when input impedance data are available rather than s11-parameter values.
 
Model Identifier: impedance
 
Parameters:
 
A table of z11-parameter values as a function of frequency
 
== Complex Modulus Block ==
 
[[File:GL59.png]]
 
This 3-pin device assumes its first and second input signals to be the real and imaginary parts of a complex signal and sends the absolute value of such a complex signal to the output with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|}
 
==Conductor-Backed CPW Line==
[[File:GK65.png]]
 
This is a four-pin, two-port device that models a conductor-backed coplanar waveguide (CPW) line segment on a single-layer dielectric substrate with a ground plane.
 
Model Identifier: cbcpw-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10.0||
|-
|}
 
==Controlled Limiter Block==
 
[[File:G35.png]]
 
The Controlled Limiter is a single-input, single-output block similar to the Gain Block. However, the output of the Controlled Limiter function is restricted to the range specified by the output lower and upper limits. This model operates in DC, AC and Transient analysis modes. Note that the limit range is the value below the Upper Limit Control input signal (CNTL_UPPER) and above the Lower Limit Control input signal (CNTL_LOWER) at which smoothing of the output signal begins. A minimum positive value of voltage difference must exist between the CNTL_UPPER and CNTL_LOWER inputs at all times. The main difference between the Controlled Limiter Block and the Limiter Block is that the former's limits are set by input control voltages, while the latter's limits are set as numerical parameters.
 
Also note that the Controlled Limiter function examines the input values of CNTL_UPPER and CNTL_LOWER to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between (cntl_upper - upper_delta - limit_range) and (cntl_lower
+ lower_delta + limit_range) and must be greater than or equal to zero. When the limit_range is specified as a fractional value, the limit_range used in the above is taken as the calculated fraction of the difference between cntl_upper and cntl_lower. Still, the potential exists for too great a limit_range value to be specified for proper operation, in which case the model will return an error message.
 
Model Identifier: climit
 
Netlist Format:
 
A&lt;device_name&gt; &lt;in_pin&gt; &lt;cntl_upper_pin&gt; &lt;cntl_lower_pin&gt; &lt;out_pin&gt; &lt;model_name&gt;
 
.model &lt;model_name&gt; climit {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 1 2 3 4 controlled_limit_block
 
.model controlled_limit_block climit in_offset = 0.0 gain = 1.0 upper_delta = 0.0 lower_delta = 0.0
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|in_offset||input offset||V||0.0||
|-
|gain||gain||-||1.0||
|-
|upper_delta||output upper delta||-||0.0||
|-
|lower_delta||output lower delta||-||0.0||
|-
|limit_range||upper and lower sm. Range||-||1.0e-6||
|-
|fraction||smoothing %/abs switch||-||False||
|-
|}
 
==Controlled One-Shot==
 
[[File:G38.png]]
 
This is an eight-terminal function generator with a single pulse output. The pulse width is controlled by an input voltage. The functional dependency of the output pulse width on the input voltage is piecewise linear and is defined as a two-dimensional table similar to a piecewise linear (PWL) controlled source. In the "pulse width vs. voltage" curve, the array "cntl_array" defines voltage values in Volts and the array "pw_array" defines the corresponding pulse width values in seconds.
 
The generation of the output pulse is triggered either on the rising or falling edge of a clock input.
 
Model Identifier: oneshot
 
Netlist Format:
 
A&lt;device_name&gt; %vd(&lt;clk_pin&gt; &lt;clk_ref_pin&gt;) %vd(&lt;cntl_in_pin&gt; &lt;cntl_in_ref_pin&gt;)
%vd(&lt;clear_pin&gt; &lt;clear_ref_pin&gt;)
%vd(&lt;out_pin&gt; &lt;out_ref_pin&gt;) &lt;model_name&gt;
 
.model &lt;model_name&gt; oneshot {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 %vd(1 5) %vd(2 6) %vd(3 7) %vd(4 8) one_shot
 
.model one_shot oneshot cntl_array = [0.0] pw_array = [1u] rise_time = 1n
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|Clk_trig||clock trigger value||V||0.5||
|-
|Pos_edge_trig||positive/negative edge trigger switch||-||True||
|-
|Cntl_array||control array||V||[0.0]||required
|-
|Pw_array||pulse width array||sec||[1u]||required
|-
|Out_low||output low value||V||0.0||
|-
|Out_high||output high value||V||1.0||
|-
|Delay||output delay from trigger||sec||1.0e-9||
|-
|Rise_time||output rise time||sec||1.0e-9||
|-
|Fall_time||output fall time||sec||1.0e-9||
|-
|}
|-
|}
 
==Controlled Sources==
Linear Voltage Controlled Voltage Source (VCVS)
 
==Controlled Square Wave Oscillator==
|-
|Rise_duty||Rise time duty cycle||0.5||
|-
|}
 
==Coplanar Strips (CPS) Line==
[[File:GK63.png]]
 
This is a four-pin, two-port device that models a coplanar strips (CPS) line segment on a single-layer conductor-backed dielectric substrate.
 
Model Identifier: cps-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||strip width||mm||2||
|-
|w||strip spacing||mm||2||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||line segment length||m||10||
|-
|}
 
==Coplanar Waveguide (CPW) Line==
[[File:G88.png]]
 
This is a four-pin, two-port device that models a coplanar waveguide (CPW) line segment on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10.0||
|-
|sigma||metal conductivity||S/m||1e10||
|-
|tand||substrate dielectric loss tangent||-||0||
|-
|t||metallization thickness||mm||0||
|-
|}
 
==Coupled Microstrip Lines==
[[File:G85.png]]
 
This is an eight-pin, four-port device that models two parallel coupled microstrip line segments on a single-layer conductor-backed dielectric substrate.
 
Model Identifier: coupled-microstrips
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||microstrip width||mm||4.8||
|-
|s||microstrip spacing||mm||5.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||microstrip length||mm||10.0||
|-
|}
 
==Coupled Striplines==
[[File:G87.png]]
 
This is an eight-pin, four-port device that models two side-by-side parallel coupled stripline segments sandwiched between two parallel plates with a dielectric spacer. In this model, the two striplines are placed at the center of the dielectric with equal distances from the top and bottom plates.
 
Model Identifier: coupled-striplines
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||microstrip width||mm||4.8||
|-
|s||microstrip spacing||mm||5.0||
|-
|b||parallel plate spacing||mm||3.2||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||stripline length||mm||10.0||
|-
|}
 
==Covered CPW Line==
[[File:GK66.png]]
 
This is a four-pin, two-port device that models a covered coplanar waveguide (CPW) line segment on a single-layer dielectric substrate without a ground backing but with a metal cover plate.
 
Model Identifier: cpw-covered
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|hc||cover height||mm||10||
|-
|len||cpw line length||mm||10||
|-
|}
 
==Covered Conductor-Backed CPW Line==
[[File:GK67.png]]
 
This is a four-pin, two-port device that models a covered conductor-backed coplanar waveguide (CPW) line segment on a single-layer dielectric substrate with both a ground plane and a metal cover plate.
 
Model Identifier: cbcpw-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|hc||cover height||mm||10||
|-
|len||cpw line length||mm||10||
|-
|}
 
==Covered Microstrip Line==
[[File:GK60.png]]
 
This is a four-pin, two-port device that models a covered microstrip line segment on a single-layer conductor-backed dielectric substrate.
 
Model Identifier: microstrip-covered
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||microstrip width||mm||4.8||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|h||cover height||mm||10||
|-
|len||microstrip length||m||10||
|-
|}
 
==CPW Gap==
[[File:G110.png]]
 
This is a four-pin, two-port device that models a gap-in-width transition between two coplanar waveguide (CPW) lines on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-gap
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|g||center strip gap spacing||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|}
 
==CPW Open End==
[[File:G108.png]]
 
This is a two-pin, one-port device that models a coplanar waveguide (CPW) line segment terminated in a open end on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-open
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||n mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10.0||
|-
|}
 
==CPW Short End==
[[File:G109.png]]
 
This is a two-pin, one-port device that models a coplanar waveguide (CPW) line segment terminated in a short end on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-short
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10.0||
|-
|}
 
==CPW Step==
[[File:G111.png]]
 
This is a four-pin, two-port device that models a step-in-width transition between two coplanar waveguide (CPW) lines of unequal widths on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-step
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||narrower slot width||mm||2.0||
|-
|s||wider center strip width||mm||2.0||
|-
|s||narrower center strip width||mm||1.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|}
 
==CPW With a Superstrate==
[[File:GK68.png]]
 
This is a four-pin, two-port device that models a coplanar waveguide (CPW) line segment on a single-layer dielectric substrate without a ground backing but with a single-layer dielectric superstrate.
 
Model Identifier: cpw-superstrate
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|hs||superstrate height||mm||1.6||
|-
|ers||superstrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10||
|-
|}
|-
|LM||motional inductance||H||100m||
|-
|}
 
==Current Limiter Block==
 
[[File:GL43.png]]
 
The Current Limiter Block models the behavior of an operational amplifier or comparator device at a high level of abstraction. All of its pins act as inputs; three of the four also act as outputs. The model takes as input a voltage value from the “in” connector. It then applies an offset and a gain, and derives from it an equivalent internal voltage (veq), which it limits to fall between pos pwr and neg pwr. If veq is greater than the output voltage seen on the “out” connector, a sourcing current will flow from the output pin. Conversely, if the voltage is less than vout, a sinking current will flow into the output pin. Depending on the polarity of the current flow, either a sourcing or a sinking resistance value (r_out_source, r_out_sink) is applied to govern the vout/i_out relationship. The chosen resistance will continue to control the output current until it reaches a maximum value specified by either i_limit_source or i_limit_sink. The latter mimics the current limiting behavior of many operational amplifier output stages. During all operation, the output current is reflected either in the pos_pwr connector current or the neg_pwr current, depending on the polarity of i_out. Thus, realistic power consumption as seen in the supply rails is included in the model. The user-specified smoothing parameters relate to model operation as follows: v_pwr_range controls the voltage below vpos_pwr and above vneg_pwr inputs beyond which veq [= gain * (vin + voffset)] is smoothed; i_source_range specifies the current below i_limit_source at which smoothing begins, as well as specifying the current increment above i_out=0.0 at
which i_pos_pwr begins to transition to zero; i_sink_range serves the same purpose with respect to i_limit_sink and i_neg_pwr that i_source_range serves for i_limit_source & i_pos_pwr; r_out_domain specifies the incremental value above and below (veq-vout)=0.0 at which r_out will be set to r_out_source and r_out_sink, respectively. For values of (veq-vout) less than r_out_domain and greater than -r_out_domain, r_out is interpolated smoothly between r_out_source & r_out_sink.
 
Model Identifier: ilimit
 
Netlist Format:
 
A&lt;device_name&gt; &lt;in_pin&gt; &lt;pos_pwr_pin&gt; &lt;neg_pwr_pin&gt; &lt;out_pin&gt; &lt;model_name&gt;
 
.model &lt;model_name&gt; ilimit {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 1 2 3 4 amp
 
.model amp ilimit in_offset=0.0 gain=16.0 r_out_source=1.0 r_out_sink=1.0 i_limit_source=1e-3 i_limit_sink=10e-3 v_pwr_range=0.2 i_source_range=1e-6 i_sink_range=1e-6 r_out_domain=1e-6
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|in_offset||input offset||V||0.0||
|-
|gain||gain||-||1.0||
|-
|r_out_source||sourcing resistance||&Omega;||1.0||
|-
|r_out_sink||sinking resistance||&Omega;||1.0||
|-
|i_limit_source||current sourcing limit||A||10m||
|-
|i_limit_sink||current sinking limit||A||10m||
|-
|v_pwr_range||power smoothing range||V||1u||
|-
|i_source_range||current sourcing smoothing range||A||1n||
|-
|i_sink_range||current sinking smoothing range||A||1n||
|-
|r_out_domain||output resistance smoothing domain||&Omega;||1n||
|-
|}
|-
|}
 
==D Flip-Flop==
 
[[File:G52.png]]
 
The digital D-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). In addition, there are asynchronous set and reset signals, which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! D !! Q !! Notes
|-
|[[File:NonRising.png]] || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Data Transfer
|-
|[[File:Rising.png]] || 1 || 1 || Data Transfer
|-
|}
</td>
</tr>
</table>
 
==D Latch==
 
[[File:G54.png]]
 
The digital D-type latch is a one-bit, level-sensitive storage element which outputs the value on the data (D) line whenever the enable (EN) input line is 1 (high). The value on the data line is stored, i.e., held on the output (Q) line whenever the enable (EN) line is 0 (low). In addition, there are set and reset signals, which are independent of the enable line. When SET = RESET = 0, the data on the D line is transferred to the output Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! EN !! D !! Q !! Notes
|-
|0 || X || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 0 || Reset
|-
|1 || 1 || 1 || Set
|-
|}
</td>
</tr>
</table>
==Darlington Pair==
|}
== DC Bias Sources Vcc, Vee, Vdd, Vss D Flip-Flop==
[[File:GL12G52.png]]
These are simple 1The digital D-pin DC voltage sourcestype flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). Vcc In addition, there are asynchronous set and Vdd provide a positive voltagereset signals, while Vee which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and Vss provide a negative voltageRESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
ParametersTruth Table:
<table><tr><td>{| class="wikitable"
|-
!NAMECLK !!PARAMETERD !!UNITQ !!DEFAULT!!NOTESNotes
|-
|vcc[[File:NonRising.png]] ||bias voltageX ||VQ<sub>prev</sub> ||+15||requiredHold State
|-
|vee[[File:Rising.png]] ||bias voltage0 ||V0 ||-15||requiredData Transfer
|-
|vdd[[File:Rising.png]] ||bias voltage1 ||V1 ||+15||required|-|vss||bias voltage||V||-15||requiredData Transfer
|-
|}
</td>
</tr>
</table>
== Delta Modulator BlockD Latch==
[[File:GL95G54.png]]
This device samples an The digital D-type latch is a one-bit, level-sensitive storage element which outputs the value on the data (D) line whenever the enable (EN) input signal at line is 1 (high). The value on the specified sampling period data line is stored, i.e., held on the output (Q) line whenever the enable (EN) line is 0 (low). In addition, there are set and generates a Delta modulated reset signals, which are independent of the enable line. When SET = RESET = 0, the data on the D line is transferred to the output signal from itQ whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
ParametersTruth Table:
<table><tr><td>{| class="wikitable"
|-
!NAMEEN !!PARAMETERD !!UNITSQ !!DEFAULT!!NOTESNotes
|-
|r_in0 ||input resistanceX ||&Omega;||1GQ<sub>prev</sub> ||Hold State
|-
|r_out1 ||output resistance0 ||&Omega;||1u0 ||Reset
|-
|T1 ||sampling period||sec1 ||1|||-|duty_cycle||sampling pulse duty cycle||-||0.01||Set
|-
|}
</td>
</tr>
</table>
== Delta-Sigma Modulator BlockDC Bias Sources Vcc, Vee, Vdd, Vss ==
[[File:GL96GL12.png]]
This device samples an input signal at the specified sampling period and generates a DeltaThese are simple 1-Sigma modulated output signal from itpin DC voltage sources.Vcc and Vdd provide a positive voltage, while Vee and Vss provide a negative voltage
Parameters:
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITSUNIT!!DEFAULT!!NOTES
|-
|r_invcc||input resistancebias voltage||&Omega;V||1G+15||required
|-
|r_outvee||output resistancebias voltage||&Omega;V||1u-15||required
|-
|Tvdd||sampling periodbias voltage||secV||1+15||required
|-
|duty_cyclevss||sampling pulse duty cycle||-||0.01|||-|} == Differential Phase Shift-Keying Modulator Block== [[File:GL94.png]] This device takes a digital input like a binary sequence and generates a DPSK modulated output signal with two specified carrier phase values. It also requires a digital clock input for synchronization.  Parameters: {| class="wikitable"|-!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES|-|r_out||output resistance||&Omega;||1u|||-|phi_lo||low carrier phase value||rad||0|||-|phi_hi||high carrier phase value||rad||&pi;|||-|fc||carrier frequency||Hz||1Meg|||-|ac||carrier peak amplitudebias voltage||V||1.0|||-|} ==Differentiator Block== [[File:G31.png]] The Differentiator Block approximates the time derivative of an input signal by calculating the incrementalslope of that signal since the previous time point. Gain and output offset parameters are also includedto allow for tailoring of the required signal. Output upper and lower limits are also included to preventconvergence erros resulting from excessively large output values. The incremental value of output belowthe output_upper_limit and above the output_lower_limit at which smoothing begins is specified via thelimit_range parameter. In AC analysis, the value returned is equal to the radian frequency of analysismultiplied by the gain. Model Identifier: d_dt Netlist Format: A&lt;device_name&gt; &lt;in_pin&gt; &lt;out_pin&gt; &lt;model_name&gt; .model &lt;model_name&gt; d_dt out_lower_limit = &lt;value&gt; out_upper_limit = &lt;value&gt; {&lt;param1 = value&gt; &lt; param2 = value&gt; ...} Example: A1 1 2 differentiator .model differentiator d_dt out_lower_limit = -1t out_upper_limit = 1t Parameters: {| class="wikitable"|-!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES|-|gain||gain||-||1.0|| |-|out_offset||output offset||V||0.0|| |-|out_lower_limit||output lower limit||V||-1t||required|-|out_upper_limit||output upper limit||V||1t||required|-|limit_range||upper and lower limit smoothing range||-||1.0e-6|| |-|} == Digital Integrator Block == [[File:GK16.png]] This device models a digital integrator with a Z-transform of -z<sup>-1/2</sup>, which is equivalent to a delay line with a delay of half the sampling period Parameters: {| class="wikitable"|-!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES|-|T||sampling period||sec||115||required
|-
|}
|-
|TNOM||parameter measurement temperature||deg C||27||
|-
|}
 
== Discrete Convolution Block ==
 
[[File:GK20.png]]
 
These blocks perform an N-point discrete convolution of their input signals. Both of the input signals x(t) and h(t) are sampled at the specified sampling period. The samples of x(t) are then shifted in time for the convolution. The output signal is a pulse train of the same period with the specified duty cycle. The input signal of these block can be either continuous-time signals or pulse trains of the specified period.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|rise_time||window rise time ||sec||0||
|-
|fall_time||window fall time ||sec||0||
|-
|duty_cycle||output pulse duty cycle||-||0.1||
|-
|gain||output gain||-||1||
|-
|}
 
== Discrete Fourier Transform (DFT) Block ==
 
[[File:GK19.png]]
 
These blocks perform an M-point discrete Fourier transform (DFT) of their input signal and then sample each period of the Fourier transform N times in the frequency domain. The output signals are two finite sequence pulse trains representing the cosine and sine DFT transforms. The input signal of these block can be either a continuous-time signal or a pulse train of the specified period.
 
There are ten DFT blocks for M = 5, 6, 7, 8, 9, 10, 12, 16, 32, 64. In each case, the total duration of the transform window is MT, where T is the sampling period. By default, the frequency domain sampling starts at t = MT and takes place over one spectral period equal to f<sub>s</sub> = 1/T. You can change the sampling start time by "n_delay" temporal periods. n_delay = 0 by default, but it can be either positive or negative. You can also extend spectral sampling to more than one spectral period by increasing the value of the parameter "n_dur", which has a default value of 1.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|N||sequence length||-||5||required
|-
|rise_time||window rise time ||sec||0||
|-
|fall_time||window fall time ||sec||0||
|-
|duty_cycle||output pulse duty cycle||-||0.1||
|-
|n_delay||number of delayed period before sampling||-||0||
|-
|n_dur||number of frequency-sampled periods||-||1||
|-
|}
 
== Discrete-Time Fourier Transform (DTFT) Block ==
 
[[File:GK18.png]]
 
These blocks perform an N-point discrete-time Fourier transform (DTFT) of their input signal and output the transform as two temporal voltage signals representing the cosine and sine DTFT transforms. The
The input signal of these block can be either a continuous-time signal or a pulse train of the specified period.
 
There are ten DTFT blocks for N = 5, 6, 7, 8, 9, 10, 12, 16, 32, 64. In each case, the total duration of the transform window is NT, where T is the sampling period.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|rise_time||window rise time ||sec||0||
|-
|fall_time||window fall time ||sec||0||
|-
|}
 
== Discrete-Time Signal Hold Block ==
 
[[File:GK14.png]]
 
This device takes a pulse train of a specified period as its input and holds the value of each pulse's amplitude during each clock cycle at the output.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|duty_cycle||sampling pulse duty cycle||-||0.1||
|-
|rise_time||window rise time ||sec||0||
|-
|fall_time||window fall time ||sec||0||
|-
|Tmax||signal period or maximum duration||sec||10||
|-
|}
 
==Divider Block==
 
[[File:G30.png]]
 
The Divider Block has two inputs. Each of the numerator and denominator inputs is added to its respective offset and then multiplied by its respective input gain (with default values of 1). Next, the loaded numerator signal is divided by the loaded denominator signal. The result is multiplied by the output gain and then added to the output offset. To avoid division by zero, the divider function sets the denominator signal greater than zero through the lower limit parameter. This limit is approached through a quadratic smoothing function, the domain of which may be specified as a fraction of the lower limit value or as an absolute value. The divider function operates in DC, AC, and Transient analysis modes. In AC analysis, however, it is important to remember that results are invalid unless the denominator input is a DC voltage.
 
Model Identifier: divide
 
Netlist Format:
 
A&lt;device_name&gt; &lt;num_pin&gt; &lt;den_pin&gt; &lt;out_pin&gt; &lt;model_name&gt;
 
.model &lt;model_name&gt; divide {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 1 2 3 divider_block
 
.model divider_block divide den_offset = 0.0 den_gain = 1.0
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|num_offset||numerator offset||V||0.0||
|-
|num_gain||numerator gain||-||1.0||
|-
|den_offset||denominator offset||V||0.0||
|-
|den_gain||denominator gain||-||1.0||
|-
|den_lower_limit||denominator lower limit||V||1.0e-10||
|-
|den_domain||denominator smoothing domain||-||1.0e-10||
|-
|fraction||smoothing fraction/absolute value switch||-||False||
|-
|out_gain||output gain||-||1.0||
|-
|out_offset||output offset||V||0.0||
|-
|}
 
==Double-Layer CPW Line==
[[File:GK69.png]]
 
This is a four-pin, two-port device that models a coplanar waveguide (CPW) line segment on a double-layer dielectric substrate without a ground backing.
 
Model Identifier: cpw-doublelayer
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|h1||lower layer substrate thickness||mm||1.6||
|-
|er1||lower layer substrate relative permittivity||-||2.2||
|-
|h2||upper layer substrate thickness||mm||1||
|-
|er2||upper layer substrate relative permittivity||-||3.0||
|-
|len||cpw line length||mm||10||
|-
|}
|-
|length||core length||m||0.01||
|-
|}
 
== Finite Sequence Pulse Generator ==
 
[[File:GL18.png]]
 
This is a voltage source that generates a pulse train of finite duration oscillating between zero and a user defined maximum voltage level.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|T||pulse period||sec||1m||required
|-
|w||pulse width||sec||0.5m||required
|-
|n||number of pulses||-||5||
|-
|rise_time||pulse rise time||sec||0||
|-
|fall_time||pulse fall time||sec||0||
|-
|max_val||maximum output voltage level||V||1||
|-|-
|start||start time||sec||0||
|-
|}
 
== Finite Sequence Random Pulse Generator ==
 
[[File:GL31.png]]
 
This is a voltage source that generates a finite sequence of random pulses with a user defined number of random levels. By default, both the pulse amplitude and pulse width are randomized. You have the option to fix either of these [[parameters]].
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|period||period||sec||1||required
|-
|duty_cycle||pulse duty cycle||-||0.5||required
|-
|random_amp||1 for random amplitude, 0 otherwise||-||1||
|-
|random_wid||1 for random pulse width, 0 otherwise||-||1||
|-
|n_rand||number of random levels||-||10||
|-
|rise_time||pulse rise time||sec||0||
|-
|fall_time||pulse fall time||sec||0||
|-
|max_val||maximum output voltage level||V||1||
|-
|n_val||number of random pulses||-||5||
|-
|start||start time||sec||0||
|-
|}
 
== Finite Sequence Signal Sampler Block ==
 
[[File:GK11.png]]
 
This device samples its input signal during a finite time window at a specified sampling period and outputs a pulse train of finite duration with a specified duty cycle.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|T||sampling period||sec||1||required
|-
|duty_cycle||sampling pulse duty cycle||-||0.01||
|-
|rise_time||window rise time ||sec||0||
|-
|fall_time||window fall time ||sec||0||
|-
|n||number of samples||-||5||
|-
|start||start time ||sec||0||
|-
|}
 
==Finite-Ground Coplanar Waveguide (FGCPW) Line==
[[File:G90.png]]
 
This is a four-pin, two-port device that models a coplanar waveguide (CPW) line segment with top ground strips of finite width on a single-layer dielectric substrate without a ground backing.
 
Model Identifier: fgcpw-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|w||slot width||mm||2.0||
|-
|s||center strip width||mm||2.0||
|-
|g||ground strip width||mm||5.0||
|-
|h||substrate thickness||mm||1.6||
|-
|er||substrate relative permittivity||-||2.2||
|-
|len||cpw line length||mm||10.0||
|-
|}
|-
|FS||signal frequency ||Hz||1||required
|-
|}
 
==Frequency Detector Block==
 
[[File:GL65.png]]
 
This device measures the frequency of a harmonic input signal and produces a voltage proportional to the frequency in Hz at the output. It can also be used as a frequency converter.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|K_v||voltage conversion factor||V/Hz||1e-6||
|-
|max_in||input amplitude||V||1||
|-
|}
 
==Frequency Doubler Block==
 
[[File:GL76.png]]
 
This device takes a harmonic input signal and generates a harmonic output signal with twice the frequency and a user specified amplitude.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|max_val||output amplitude||V||1.0||
|-
|}
 
== Frequency Down-Converter Block==
 
[[File:GL80.png]]
 
This 3-pin device takes two harmonic input signals with different frequencies f<sub>LO</sub> and f<sub>IF</sub> and generates a harmonic output signal with a frequency equal to f<sub>RF</sub> = f<sub>LO</sub> - f<sub>IF</sub> and a user specified amplitude.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|max_in||peak amplitude of both inputs||V||1.0||Both inputs must have equal amplitudes.
|-
|max_out||output amplitude||V||1.0||
|-
|}
The only parameter is the scale factor SF with a default value of 1.0. Set SF = 1e-6 to read out the frequency in MHz. Set SF = 1e-9 to read out the frequency in GHz. Set SF = 6.283185 (2*pi) to read out the angular frequency &omega; in radian/s.
 
== Frequency Modulator Block==
 
[[File:GL88.png]]
 
This device takes an input signal and generates an FM modulated output signal of a specified carrier frequency with a specified maximum frequency deviation.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|f_del||maximum frequency deviation||Hz||500k||
|-
|fc||carrier frequency||Hz||1Meg||
|-
|ac||carrier peak amplitude||V||1||
|-
|}
 
== Frequency Shift-Keying Modulator Block==
 
[[File:GL92.png]]
 
This device takes a digital input like a binary sequence and generates an FSK modulated output signal with two specified carrier frequencies.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_out||output resistance||&Omega;||1u||
|-
|fc_lo||low carrier frequency||Hz||1Meg||
|-
|fc_hi||high carrier frequency||Hz||2Meg||
|-
|ac||carrier peak amplitude||V||1.0||
|-
|}
 
== Frequency Up-Converter Block==
 
[[File:GL79.png]]
 
This 3-pin device takes two harmonic input signals with different frequencies f<sub>LO</sub> and f<sub>IF</sub> and generates a harmonic output signal with a frequency equal to f<sub>RF</sub> = f<sub>LO</sub> + f<sub>IF</sub> and a user specified amplitude.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|max_in||peak amplitude of both inputs||V||1.0||both inputs must have equal amplitudes.
|-
|max_out||output amplitude||V||1.0||
|-
|}
== Fuse ==
|-
|i_thresh||threshold current||A||1.0||
|-
|}
 
==Gain Block==
 
[[File:G27.png]]
 
This model is a simple gain block with optional offsets on the input and the output. In_offset is added
to the input, the sum of which is then multiplied by the gain, and the output offset is added to produce
the final output. The gain block model will operate in DC, AC, and Transient analysis modes.
 
Model Identifier: gain
 
Netlist Format:
 
A&lt;device_name&gt; &lt;in_pin&gt; &lt;out_pin&gt; &lt;model_name&gt;
 
.model &lt;model_name&gt; gain {&lt;param1 = value&gt; &lt; param2 = value&gt; ...}
 
Example:
 
A1 1 2 gain_block
 
.model gain_block gain in_offset = 0.0 out_offset = 0.0
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|in_offset||input offset||V||0.0||
|-
|gain||gain||-||1.0||
|-
|out_offset||out_offset||V||0.0||
|-
|}
 
==Generalized Analog Filter Block==
 
[[File:GL85.png]]
 
This block models a generalize analog filter characterized by a rational transfer functions in the spectral domain Laplace variable s:
 
<math> H(s) = \frac{N(s)}{D(s)} = \frac{ \sum_{m=0}^{M} b_m s^m }{ \sum_{n=0}^{N} a_n s^n } </math>
 
subject to the requirement N &ge; M and a<sub>N</sub> = 1. To access the parameters of this block, you have to click the {{key|Edit Model...}} button of its property dialog.
 
The functionality of this block, which is native to [[RF.Spice A/D]], is very similar to the s-domain transfer function block, which is an XPSICE process model. This block does not have a denormalization frequency parameter. Therefore, at frequencies other than the unit frequency, the transfer function must be explicitly scaled. This block can be used in conjunction with both transient and AC frequency sweep tests.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|deg||highest degree of s in transfer function||-||2||required
|-
|coeff_den||denominator coefficients array: coefficients of powers of s, highest power first||-||1 0 1||required
|-
|coeff_num||numerator coefficients array: coefficients of powers of s, highest power first||-||0 0 1||required
|-
|r_in||input resistance||&Omega;||10G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|}
 
==Generalized Digital Filter Block==
 
[[File:GK17.png]]
 
This block models a generalized digital filter characterized by a rational transfer functions in the Z-transform domain variable z:
 
<math> H(z) = \frac{N(z)}{D(z)} = \frac{ \sum_{m=0}^{M} b_m z^m }{ \sum_{n=0}^{N} a_n z^n } </math>
 
subject to the requirement N &ge; M. To access the parameters of this block, you have to click the {{key|Edit Model...}} button of its property dialog.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|deg||highest degree of z in transfer function||-||2||required
|-
|coeff_den||denominator coefficients array: coefficients of powers of (-z<sup>1/2</sup>), highest power first||-||1 0 1 0 1||required
|-
|coeff_num||numerator coefficients array: coefficients of powers of (-z<sup>1/2</sup>), highest power first||-||1 0 0 0 0||required
|-
|freq||sampling frequency||Hz||1||required
|-
|}
 
== Generic Bandpass Filter Block==
 
[[File:GL83.png]]
 
This device is a generic bandpass filter with user specified center frequency and bandwidth. It is based on a fifth-order Butterworth LC ladder topology.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|f0||center frequency||Hz||1Meg||
|-
|bw||bandwidth||Hz||200k||
|-
|r0||source/load resistance||&Omega;||50||
|-
|}
 
== Generic Bandstop Filter Block==
 
[[File:GL84.png]]
 
This device is a generic bandstop filter with user specified center frequency and bandwidth. It is based on a fifth-order Butterworth LC ladder topology.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|f0||center frequency||Hz||1Meg||
|-
|bw||bandwidth||Hz||200k||
|-
|r0||source/load resistance||&Omega;||50||
|-
|}
 
==Generic Bend Junction==
[[File:G65.png]]
 
This is a four-pin, two-port device that models a bend in a general purpose transmission line. The bend geometry and the line structure can be very complicated, and their full-wave effects can be captured by the measured or simulated S-parameter data of this device. The model may also include a certain length of the transmission line at the input and output ports.
 
Model Identifier: bend-junction
 
Parameters:
 
A table of s11, s21, s12 and s22-parameter values as a function of frequency
 
==Generic Coupled T-Lines==
[[File:G72.png]]
 
This is an eight-pin, four-port device that models a two parallel general purpose coupled transmission line segments. Ports 1 and 2 represent the input and output of the first T-Line. Ports 3 and 4 represent the input and output of the second coupled T-Line.
 
Model Identifier: coupled-lines
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Z0e||even mode characteristic impedance||Ohms||50.0||
|-
|Z0o||odd mode characteristic impedance||Ohms||10.0||
|-
|eeff||effective permittivity||-||1.0||
|-
|len||line segment length||mm||10.0||
|-
|}
 
==Generic Cross Junction==
[[File:G68.png]]
 
This is an eight-pin, four-port device that models a cross junction among four general purpose transmission lines. The cross geometry and the line structures can be very complicated, and their full-wave effects can be captured by the measured or simulated S-parameter data of this device. The model may also include a certain length of the four transmission lines at the four ports.
 
Model Identifier: tee-junction
 
Parameters:
 
A table of s11, s21, s31, s41, s12, s22, s32, s42, s13, s23, s33, s43, s14, s24, s34 and s44-parameter values as a function of frequency
 
== Generic Highpass Filter Block==
 
[[File:GL82.png]]
 
This device is a generic highpass filter with a user specified cutoff frequency. It is based on a fifth-order Butterworth LC ladder topology.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|cutoff||cutoff frequency||Hz||1Meg||
|-
|r0||source/load resistance||&Omega;||50||
|-
|}
 
== Generic Lowpass Filter Block==
[[File:GL81.png]]
 
This device is a generic lowpass filter with a user specified cutoff frequency. It is based on a fifth-order Butterworth LC ladder topology.
 
[[Parameters]]:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|cutoff||cutoff frequency||Hz||1Meg||
|-
|r0||source/load resistance||&Omega;||50||
|-
|}
 
==Generic Multiport Networks==
[[File:G60.png]] [[File:G61.png]] [[File:G62.png]] [[File:G63.png]]
 
[[RF.Spice A/D]] currently offers four types of generic network devices: one-port, two-port, three-port and four-port. There are two-pin, four-pin, six-pin and eight-pin, respectively. [[Multiport Networks|Multiport networks]] can be used to model very complicated active or passive structures, which can be characterized by their measured or simulated S-parameter data.
 
Model Identifier: one-port, two-port, three-port, four-port
 
Parameters:
 
One-Port: A table of s11-parameter values as a function of frequency
 
Two-Port: A table of s11, s21, s12 and s22-parameter values as a function of frequency
 
Three-Port: A table of s11, s21, s31, s12, s22, s32, s13, s23 and s33-parameter values as a function of frequency
 
Four-Port: A table of s11, s21, s31, s41, s12, s22, s32, s42, s13, s23, s33, s43, s14, s24, s34 and s44-parameter values as a function of frequency
 
==Generic Open End==
[[File:G64.png]]
 
This is a two-pin, one-port device that models the open end of a general purpose transmission line segment. Infringing capacitance effects can be captured by the measured or simulated S-parameter data of this device. The model may also include a certain length of the transmission line.
 
Model Identifier: open-end
 
Parameters:
 
A table of s11-parameter values as a function of frequency
 
==Generic Open Stub==
[[File:G70.png]]
 
This is a two-pin, one-port device that models a general purpose transmission line segment terminated in an open end. An infinite impedance load is indeed connected to the end of the T-line segment. The fringing capacitance effects, however, are neglected by this model.
 
Model Identifier: stub-open
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Z0||characteristic impedance||Ohms||50.0||
|-
|eeff||effective permittivity||-||1.0||
|-
|alpha||attenuation constant||dB/m||0.0||
|-
|len||line segment length||mm||10.0||
|-
|}
 
==Generic Short Stub==
[[File:G71.png]]
 
This is a two-pin, one-port device that models a general purpose transmission line segment terminated in a shorted end. A zero impedance load is indeed connected to the end of the T-line segment. The inductive loading effects, however, are neglected by this model.
 
Model Identifier: stub-short
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Z0||characteristic impedance||Ohms||50.0||
|-
|eeff||effective permittivity||-||1.0||
|-
|alpha||attenuation constant||dB/m||0.0||
|-
|len||line segment length||mm||10.0||
|-
|}
 
==Generic Step Junction==
[[File:G66.png]]
 
This is a four-pin, two-port device that models a step-in-width junction between two general purpose transmission lines. The step geometry and the line structures can be very complicated, and their full-wave effects can be captured by the measured or simulated S-parameter data of this device. The model may also include a certain length of the two transmission lines at the input and output ports.
 
Model Identifier: step-junction
 
Parameters:
 
A table of s11, s21, s12 and s22-parameter values as a function of frequency
 
==Generic T-Line==
[[File:G69.png]]
 
This is a four-pin, two-port device that models a general purpose transmission line segment.
 
Model Identifier: t-line
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|Z0||characteristic impedance||Ohms||50.0||
|-
|eeff||effective permittivity||-||1.0||
|-
|alpha||attenuation constant||dB/m||0.0||
|-
|len||line segment length||mm||10.0||
|-
|}
 
==Generic Tee Junction==
[[File:G67.png]]
 
This is a six-pin, three-port device that models a tee junction among three general purpose transmission lines. The tee geometry and the line structures can be very complicated, and their full-wave effects can be captured by the measured or simulated S-parameter data of this device. The model may also include a certain length of the three transmission lines at the two through ports and the side arm.
 
Model Identifier: tee-junction
 
Parameters:
 
A table of s11, s21, s31, s12, s22, s32, s13, s23 and s33-parameter values as a function of frequency
 
== Geometric Mean Block ==
 
[[File:GL57.png]]
 
This 3-pin device sends the geometric mean of its two inputs to the output with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|gain||gain||-||1.0||
|-
|}
you may use in a circuit. All components connected to ground are referenced to a common point and treated
as linked through ground.
 
==Gudermannian Polarity Detector Block==
 
[[File:GL68.png]]
 
This 3-pin device measures the difference signal &Delta;v = v<sub>pos</sub> - v<sub>neg</sub> and produces an output proportional to the Gudermannian function of &Delta;v:
 
<math> v_{out} = A \cdot \frac{2}{\pi} \ gd(a\Delta v) = A \cdot \left( \frac{4}{\pi} \tan^{-1}(e^{a\Delta v}) - 1 \right) </math>
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|a||shaping Constant||-||10||
|-
|MaxVal||output amplitude||V||1||
|-
|}
==Hysteresis Block (XSPICE)==
|-
|fraction||smoothing fraction/absolute value switch||true
|-
|}
 
==Ideal Buffer Block==
 
[[File:GL40.png]]
 
This model is an ideal buffer block with a default unity gain.
 
Parameters:
 
{| class="wikitable"
|-
!NAME!!PARAMETER!!UNITS!!DEFAULT!!NOTES
|-
|r_in||input resistance||&Omega;||1G||
|-
|r_out||output resistance||&Omega;||1u||
|-
|gain||gain||-||1.0||
|-
|}
where v<sub>P</sub> is the primary voltage, v<sub>S1</sub> is measured between the top secondary pin S1 and the center tap pin, and v<sub>S2</sub> is measured between the center tap pin and the bottom secondary pin S2. The red dots show the polarity of the windings on each side. This model has one parameter: ratio = n = N<sub>P</sub>/N<sub>S1</sub> = N<sub>P</sub>/N<sub>S2</sub>, which represents the primary-to-secondary (half-winding) turns ratio.
 
==Ideal Circulator==
[[File:G79.png]] [[File:G80.png]]
 
This is a six-pin, three-port device that models an ideal microwave circulator. There are two types of this device: Clockwise Circulator and Counterclockwise Circulator . The ideal circulator model is a simple non-reciprocal 3&times;3 scattering matrix fixed over all frequencies.
 
Model Identifier: circulator_cw & circulator_ccw
 
Parameters: None
==Ideal Diode==
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