Changes

RF.Spice A/D Glossary

2,659 bytes added, 15:11, 7 October 2024
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==D Flip-Flop==
 
[[File:G52.png]]
 
The digital D-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). In addition, there are asynchronous set and reset signals, which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! D !! Q !! Notes
|-
|[[File:NonRising.png]] || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Data Transfer
|-
|[[File:Rising.png]] || 1 || 1 || Data Transfer
|-
|}
</td>
</tr>
</table>
 
==D Latch==
 
[[File:G54.png]]
 
The digital D-type latch is a one-bit, level-sensitive storage element which outputs the value on the data (D) line whenever the enable (EN) input line is 1 (high). The value on the data line is stored, i.e., held on the output (Q) line whenever the enable (EN) line is 0 (low). In addition, there are set and reset signals, which are independent of the enable line. When SET = RESET = 0, the data on the D line is transferred to the output Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! EN !! D !! Q !! Notes
|-
|0 || X || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 0 || Reset
|-
|1 || 1 || 1 || Set
|-
|}
</td>
</tr>
</table>
==Darlington Pair==
|}
== DC Bias Sources Vcc, Vee, Vdd, Vss D Flip-Flop==
[[File:GL12G52.png]]
These are simple 1The digital D-pin DC voltage sourcestype flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). Vcc In addition, there are asynchronous set and Vdd provide a positive voltagereset signals, while Vee which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and Vss provide a negative voltageRESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
ParametersTruth Table:
<table><tr><td>{| class="wikitable"
|-
!NAMECLK !!PARAMETERD !!UNITQ !!DEFAULT!!NOTESNotes
|-
|vcc[[File:NonRising.png]] ||bias voltageX ||VQ<sub>prev</sub> ||+15||requiredHold State
|-
|vee[[File:Rising.png]] ||bias voltage0 ||V0 ||-15||requiredData Transfer
|-
|vdd[[File:Rising.png]] ||bias voltage1 ||V1 ||+15||required|-|vss||bias voltage||V||-15||requiredData Transfer
|-
|}
</td>
</tr>
</table>
==Digital BufferD Latch==
[[File:G57G54.png]]
The digital buffer D-type latch is a singleone-inputbit, singlelevel-output digital device sensitive storage element which produces as output a time-delayed copy of its outputs the value on the data (D) line whenever the enable (EN) inputline is 1 (high). The delays associated with value on the output rise and fall may be differentdata line is stored, i. The model also posts an input load value e., held on the output (in FaradsQ) line whenever the enable (EN) line is 0 (low). The output of this model does NOTIn addition, howeverthere are set and reset signals, which are independent of the enable line. When SET = RESET = 0, respond to the total loading it sees data on its output; it will always drive the output strongly with D line is transferred to the specified delaysoutput Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
==Digital Clock==Truth Table:
[[File:G56.png]]<table><tr>The digital clock provides a periodic pulsing input for many other digital devices. Its parameters include the period and pulse width, both expressed in seconds. The pulse width is the time interval during which the clock's output signal is at its logic high level. ==Digital Frequency Divider Block== [[File:GK49.png]] The digital frequency divider is a programmable step-down divider which accepts an arbitrary divisor (div_factor), a duty cycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently. Parameters:<td>{| class="wikitable"
|-
!NAMEEN !!PARAMETERD !!UNITQ !!DEFAULT!!NOTESNotes
|-
|div_factor0 ||divide factorX ||-Q<sub>prev</sub> ||2||requiredHold State
|-
|high_cycles1 ||number of high clock cycles0 ||-||10 ||Reset
|-
|i_count1 ||output initial count value1 ||-||0|||-|rise_delay||L-to-H delay time||sec||1p|| |-|fall_delay||H-to-L delay time||sec||1p|| |-|freq_in_load||freq_in capacitive load value||F||1p1 || Set
|-
|}
</td>
</tr>
</table>
==Digital InputDC Bias Sources Vcc, Vee, Vdd, Vss ==
[[File:GK46GL12.png]]
The digital input provides the easiest way of defining input data in [[RF.Spice A/D]]. The data is These are simple 1-bit and in decimal format by defaultpin DC voltage sources. You can define multi-bit data as well as a hexadecimal format. The value of the input can be entered either in the device's property dialog or directly in the Schematic Editor using the up Vcc and down arrows of the device symbol. ==Digital Oscillator== [[File:GK41.png]] The digital oscillator is a mixed-mode device which accepts as input Vdd provide a analog positive voltage signal. This input is compared to the voltage-to-frequency transfer characteristic specified by the (cntl_array, freq_array) coordinate pairs, while Vee and Vss provide a frequency is obtained which represents a linear interpolation or extrapolation based on those pairs. A digital time-varying signal is then produced with this fundamental frequency. The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays which can be specified independently. In addition, the duty cycle and the phase of the waveform are also variable and can be set by you. Example SPICE Usage:a5 1 8 var_clock.model var_clock d_osc cntl_array = [-2 -1 1 2] freq_array = [1e3 1e3 10e3 10e3] duty_cycle = 0.4 init_phase = 180.0 rise_delay = 10e-9 fall_delay=8e-9)negative voltage
Parameters:
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|cntl_arrayvcc||control arraybias voltage||V||[0.0]+15||required
|-
|freq_arrayvee||frequency arraybias voltage||HzV||[1u]-15||required
|-
|duty_cyclevdd||output duty cyclebias voltage||-V||0.5+15|| required
|-
|init_phasevss||intial phase of outputbias voltage||degV||0|| |-|rise_delay||rise delay time||sec||1n|| |-|fall_delay||fall delay time||sec||1n15|| required
|-
|}
 
==Digital Output==
 
[[File:GK47.png]]
 
The digital output provides the easiest way of displaying output data in [[RF.Spice A/D]]. The data is in decimal format by default. You can display it in the hexadecimal format.
 
==Digital Probe==
 
[[File:GK48.png]]
 
The digital probe is very similar to digital output but does not display the value of the data. It is intended as an output signal designator for transient [[tests]].
 
==Digital Source==
 
[[File:GK40.png]]
 
The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The device reads input from a table or an input file and, at the times specified, and generates the inputs along with the strengths listed. The data is 1-bit and in decimal format by default. You can define multi-bit data as well as a hexadecimal format. You can also make the data periodic with a specified period in seconds or define an initial delay in seconds.
 
The format of the input file is as shown below:
 
&lowast; time value
 
0 0
 
10n 1
 
20n 1
 
30n 0
 
40n 1
 
50n 0
==Digital-to-Analog Converter (DAC) Bridge==
This device is an interactive switch that can be closed or opened either directly from the Schematic Editor by clicking on its symbol or from the Instrument Panel.
 
==JK Flip-Flop==
 
[[File:G53.png]]
 
The digital JK-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). If J = 1 and K = 0, then the output is set (i.e. Q = 1) on the rising edge of the clock. If J = 0 and K = 1, then the output is reset (i.e. Q = 0). If J = K = 0, then the outputs do not change. If J = K = 1, then the outputs toggle on the positive edge of the clock signal. In addition, there are asynchronous set and reset signals, which are independent of the clock. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! J !! K !! Q !! Notes
|-
|[[File:NonRising.png]] || X || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 1 || 0 || Reset
|-
|[[File:Rising.png]] || 1 || 0 || 1 || Set
|-
|[[File:Rising.png]] || 1 || 1 || NOT(Q<sub>prev</sub>) || Toggle
|-
|}
</td>
</tr>
</table>
==Junction Field Effect Transistor (JFET)==
E1 1 0 2 0 1.0
 
==Logic AND Gate==
 
[[File:G43.png]]
 
The AND gate performs the logical function Y = A & B. The AND function's output is one (high) if all of the inputs are one, and zero (low) otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .AND. B
|-
|0 || 0 || 0
|-
|0 || 1 || 0
|-
|1 || 0 || 0
|-
|1 || 1 || 1
|-
|}
</td>
</tr>
</table>
 
==Logic Inverter Gate==
 
[[File:G49.png]]
 
The Inverter performs the logical function Y = NOT(A). The Inverter function's output is one (high) if the input is zero (low), and vice versa.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! .NOT. A
|-
|0 || 1
|-
|1 || 0
|-
|}
</td>
</tr>
</table>
 
==Logic NAND Gate==
 
[[File:G44.png]]
 
The NAND gate is just the inverse of the AND function: Y = NOT(A & B) = NOT(A) | NOT(B). The NAND function's output is zero (low) if all of the inputs are one (high), and one otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .NAND. B
|-
|0 || 0 || 1
|-
|0 || 1 || 1
|-
|1 || 0 || 1
|-
|1 || 1 || 0
|-
|}
</td>
</tr>
</table>
==Logic NOR Gate==
 
[[File:G46.png]]
 
The NOR gate is just the inverse of the OR function: Y = NOT(A | B) = NOT(A) & NOT(B). The NOR function's output is zero (low) if one or more of the inputs are one (high), and one otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .NOR. B
|-
|0 || 0 || 1
|-
|0 || 1 || 0
|-
|1 || 0 || 0
|-
|1 || 1 || 0
|-
|}
</td>
</tr>
</table>
==Logic OR Gate==
 
[[File:G45.png]]
 
The OR gate performs the logical function Y = A | B. The OR function's output is one (high) if one or more inputs are one, and zero (low) otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .OR. B
|-
|0 || 0 || 0
|-
|0 || 1 || 1
|-
|1 || 0 || 1
|-
|1 || 1 || 1
|-
|}
</td>
</tr>
</table>
==Logic XOR Gate==
 
[[File:G47.png]]
 
The XOR gate performs the logical Exclusive OR function Y = A &oplus; B. The XOR function's output is one (high) if one and only one input is one, and zero (low) otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .XOR. B
|-
|0 || 0 || 0
|-
|0 || 1 || 1
|-
|1 || 0 || 1
|-
|1 || 1 || 0
|-
|}
</td>
</tr>
</table>
 
==Logic XNOR Gate==
 
[[File:G48.png]]
 
The OR gate performs the logical function Y = NOT(A &oplus; B). The XNOR function's output is one (high) if and only if all of the inputs have the same state, and zero (low) otherwise.
<table>
<tr>
<td>
{| class="wikitable"
|-
! A !! B !! A .XNOR. B
|-
|0 || 0 || 1
|-
|0 || 1 || 0
|-
|1 || 0 || 0
|-
|1 || 1 || 1
|-
|}
</td>
</tr>
</table>
==Lossless Transmission Line==
|-
|}
 
== Pseudo-Random Bit Sequence Generator==
 
[[File:GK39.png]]
 
This device outputs a random binary bit at each clock cycle.
 
Parameters:
 
None
==Random Resistor==
|-
|}
 
==SR Flip-Flop==
 
[[File:G59.png]]
 
The digital SR-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). The value stored on the output Q line will depend on the S and R input line values. If S = 1 and R = 0, the output is set (i.e. Q = 1) on the rising edge of the clock. If S = 0 and R = 1, the output is reset (i.e. Q = 0) on the rising edge of the clock. If both inputs are S = R = 0, then the outputs do not change from the previous state. If both inputs are S = R = 1, then the result is unknown. In addition, there are asynchronous set and reset signals, which are independent of the clock input. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0.
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! S !! R !! Q !! Notes
|-
|[[File:NonRising.png]] || X || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 1 || 0 || Reset
|-
|[[File:Rising.png]] || 1 || 0 || 1 || Set
|-
|[[File:Rising.png]] || 1 || 1 || X || Illegal
|-
|}
</td>
</tr>
</table>
 
==SR Latch==
 
[[File:G58.png]]
 
The digital SR-type latch is a one-bit, level-sensitive storage element which outputs the value dictated by the state of the S and R input lines whenever the enable (EN) input line is 1 (high). This value is stored (i.e., held on the output line) whenever the enable (EN) line is 0 (low). If S = 1 and R = 0, the latch is set (i.e. Q = 1). If S = 0 and R = 1, the latch is reset (i.e. Q = 0). If both inputs are S = R = 0, then the outputs do not change from the previous state. If both inputs are S = R = 1, then the result is unknown. In addition, there are set and reset signals, which are independent of the enable line. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! EN !! S !! R !! Q !! Notes
|-
|0 || X || X || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 0 || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 1 || 0 || Reset
|-
|1 || 1 || 0 || 1 || Set
|-
|1 || 1 || 1 || X || Illegal
|-
|}
</td>
</tr>
</table>
==Tabulated Conductor==
This device has no parameters.
==Toggle Flip-Flop==
 
[[File:G55.png]]
 
The digital T-type flip-flop is a one-bit, edge-triggered storage element which toggles its current state whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). When the toggle (T) line is zero, the flip-flop is inactive. When T is high, the flip-flop's output toggles its value on the rising edge of the clock. In addition, there are asynchronous set and reset signals, which are independent of the clock input. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! T !! CLK !! Q !! Notes
|-
|0 || X || Q<sub>prev</sub> || Hold State
|-
|1 || [[File:NonRising.png]] || Q<sub>prev</sub> || Hold State
|-
|1 || [[File:Rising.png]] || NOT(Q<sub>prev</sub>) || Toggle
|-
|}
</td>
</tr>
</table>
== Triac Thyristor ==
Asabet
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