Changes

RF.Spice A/D Glossary

4,249 bytes added, 15:05, 7 October 2024
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==D Flip-Flop==
 
[[File:G52.png]]
 
The digital D-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high). In addition, there are asynchronous set and reset signals, which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! CLK !! D !! Q !! Notes
|-
|[[File:NonRising.png]] || X || Q<sub>prev</sub> || Hold State
|-
|[[File:Rising.png]] || 0 || 0 || Data Transfer
|-
|[[File:Rising.png]] || 1 || 1 || Data Transfer
|-
|}
</td>
</tr>
</table>
 
==D Latch==
 
[[File:G54.png]]
 
The digital D-type latch is a one-bit, level-sensitive storage element which outputs the value on the data (D) line whenever the enable (EN) input line is 1 (high). The value on the data line is stored, i.e., held on the output (Q) line whenever the enable (EN) line is 0 (low). In addition, there are set and reset signals, which are independent of the enable line. When SET = RESET = 0, the data on the D line is transferred to the output Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.
 
Truth Table:
 
<table>
<tr>
<td>
{| class="wikitable"
|-
! EN !! D !! Q !! Notes
|-
|0 || X || Q<sub>prev</sub> || Hold State
|-
|1 || 0 || 0 || Reset
|-
|1 || 1 || 1 || Set
|-
|}
</td>
</tr>
</table>
==Darlington Pair==
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==D Flip-FlopDC Bias Sources Vcc, Vee, Vdd, Vss ==
[[File:G52GL12.png]]
The digital DThese are simple 1-type flip-flop is a one-bit, edge-triggered storage element which stores data whenever the clock (CLK) input line transitions from 0 (low) to 1 (high)pin DC voltage sources. In addition, there are asynchronous set Vcc and reset signalsVdd provide a positive voltage, which are independent of the clock. When SET = RESET = 0, the data on the D line is transferred to the output Q on the rising edge of the clock. The combination SET = 1 while Vee and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1.Vss provide a negative voltage
Truth TableParameters:
<table><tr><td>{| class="wikitable"
|-
! CLK NAME!! D PARAMETER!! Q UNIT!! NotesDEFAULT!!NOTES
|-
|[[File:NonRising.png]] vcc|| X bias voltage|| Q<sub>prev</sub> V|| Hold State+15||required
|-
|[[File:Rising.png]] vee|| 0 bias voltage|| 0 V|| Data Transfer-15||required
|-
|[[File:Rising.png]] vdd|| 1 bias voltage|| 1 V|| Data Transfer+15||required|-|vss||bias voltage||V||-15||required
|-
|}
</td>
</tr>
</table>
==D LatchDigital Buffer==
[[File:G54G57.png]]
The digital D-type latch buffer is a onesingle-bitinput, levelsingle-sensitive storage element output digital device which outputs the value on the data (D) line whenever the enable (EN) produces as output a time-delayed copy of its input line is 1 (high). The value on delays associated with the data line is stored, ioutput rise and fall may be different.e., held on the output The model also posts an input load value (Q) line whenever the enable (EN) line is 0 (lowin Farads). In additionThe output of this model does NOT, there are set and reset signals, which are independent of the enable line. When SET = RESET = 0however, respond to the data total loading it sees on its output; it will always drive the D line is transferred to output strongly with the output Q whenever EN = 1. The combination SET = 1 and RESET = 0, causes Q = 1. The combination SET = 0 and RESET = 1 causes Q = 0. The combination SET = RESET = 1 is illegal and is resolved by setting both outputs Q and Q_bar to 1specified delays.
Truth Table: ==Digital Clock==
<table>[[File:G56.png]]<tr><td>The digital clock provides a periodic pulsing input for many other digital devices. Its parameters include the period and pulse width, both expressed in seconds. The pulse width is the time interval during which the clock's output signal is at its logic high level. ==Digital Frequency Divider Block== [[File:GK49.png]] The digital frequency divider is a programmable step-down divider which accepts an arbitrary divisor (div_factor), a duty cycle term (high_cycles), and an initial count value (i_count). The generated output is synchronized to the rising edges of the input signal. Rise delay and fall delay on the outputs may also be specified independently. Parameters: {| class="wikitable"
|-
! EN NAME!! D PARAMETER!! Q UNIT!! NotesDEFAULT!!NOTES
|-
|0 div_factor|| X divide factor|| Q<sub>prev</sub> -|| Hold State2||required
|-
|1 high_cycles|| 0 number of high clock cycles|| 0 -||1|| Reset
|-
|1 i_count|| 1 output initial count value|| 1 -||0|||-|rise_delay||L-to-H delay time||sec||1p|| |-|fall_delay||H-to-L delay time||sec||1p|| |-|freq_in_load||freq_in capacitive load value||F||1p|| Set
|-
|}
</td>
</tr>
</table>
== DC Bias Sources Vcc, Vee, Vdd, Vss Digital Input==
[[File:GL12GK46.png]]
These are simple The digital input provides the easiest way of defining input data in [[RF.Spice A/D]]. The data is 1-pin DC voltage sourcesbit and in decimal format by default. Vcc You can define multi-bit data as well as a hexadecimal format. The value of the input can be entered either in the device's property dialog or directly in the Schematic Editor using the up and Vdd provide down arrows of the device symbol. ==Digital Oscillator== [[File:GK41.png]] The digital oscillator is a mixed-mode device which accepts as input a positive analog voltagesignal. This input is compared to the voltage-to-frequency transfer characteristic specified by the (cntl_array, freq_array) coordinate pairs, while Vee and Vss provide a negative voltagefrequency is obtained which represents a linear interpolation or extrapolation based on those pairs. A digital time-varying signal is then produced with this fundamental frequency. The output waveform, which is the equivalent of a digital clock signal, has rise and fall delays which can be specified independently. In addition, the duty cycle and the phase of the waveform are also variable and can be set by you. Example SPICE Usage:a5 1 8 var_clock.model var_clock d_osc cntl_array = [-2 -1 1 2] freq_array = [1e3 1e3 10e3 10e3] duty_cycle = 0.4 init_phase = 180.0 rise_delay = 10e-9 fall_delay=8e-9)
Parameters:
!NAME!!PARAMETER!!UNIT!!DEFAULT!!NOTES
|-
|vcccntl_array||bias voltagecontrol array||V||+15[0.0]||required
|-
|veefreq_array||bias voltagefrequency array||VHz||-15[1u]||required
|-
|vddduty_cycle||bias voltageoutput duty cycle||V-||+150.5||required
|-
|vssinit_phase||bias voltageintial phase of output||Vdeg||0|| |-15|rise_delay||rise delay time||sec||1n|| |-|fall_delay||fall delay time||sec||1n||required
|-
|}
 
==Digital Output==
 
[[File:GK47.png]]
 
The digital output provides the easiest way of displaying output data in [[RF.Spice A/D]]. The data is in decimal format by default. You can display it in the hexadecimal format.
 
==Digital Probe==
 
[[File:GK48.png]]
 
The digital probe is very similar to digital output but does not display the value of the data. It is intended as an output signal designator for transient [[tests]].
 
==Digital Source==
 
[[File:GK40.png]]
 
The digital source provides for straightforward descriptions of digital signal vectors in a tabular format. The device reads input from a table or an input file and, at the times specified, and generates the inputs along with the strengths listed. The data is 1-bit and in decimal format by default. You can define multi-bit data as well as a hexadecimal format. You can also make the data periodic with a specified period in seconds or define an initial delay in seconds.
 
The format of the input file is as shown below:
 
&lowast; time value
 
0 0
 
10n 1
 
20n 1
 
30n 0
 
40n 1
 
50n 0
==Digital-to-Analog Converter (DAC) Bridge==
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